MCIMX255AJM4AR2 Freescale Semiconductor, MCIMX255AJM4AR2 Datasheet - Page 55

• Manufacturer Part Number: MCIMX255AJM4AR2
• Description: Processors - Application Specialized IMX25 1.2 AUTO
• Manufacturer: Freescale Semiconductor

Specifications of MCIMX255AJM4AR2

• Core: ARM926EJ-S
• Processor Series: MCIMX25
• Maximum Clock Frequency: 400 MHz
• Instruction / Data Cache Memory: 16 KB
• Data Ram Size: 128 KB
• Operating Supply Voltage: 1.15 V to 1.52 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: MAPBGA-400
• Interface Type: USB
• Memory Type: DDR2
• Minimum Operating Temperature: - 40 C

1
2
3
4
5
3.7.6
The EMI module includes the enhanced SDRAM/LPDDR memory controller (ESDCTL), NAND Flash
controller (NFC), and wireless external interface module (WEIM). The following subsections give timing
information for these submodules.
Freescale Semiconductor
The output SCLK transition time is tested with 25 pF drive.
T
T
T
T
wait
sclk
per
ipg
t10
t11
t12
t13
t14
t1’
t2’
t3’
t5’
t6’
t7’
ID
t1
t2
t3
t4
t5
t6
t7
t8
t9
= CSPI main clock IPG_CLOCK period
= CSPI reference baud rate clock period (PERCLK2)
= Wait time, as specified in the sample period control register
= CSPI clock period
CSPI master SCLK cycle time
CSPI master SCLK high time
CSPI master SCLK low time
CSPI slave SCLK cycle time
CSPI slave SCLK high time
CSPI slave SCLK low time
CSPI SCLK transition time
SS n output pulse width
SS n input pulse width
SS n output asserted to first SCLK edge (SS output setup
time)
SS n input asserted to first SCLK edge (SS input setup
time)
CSPI master: Last SCLK edge to SS n negated (SS
output hold time)
CSPI slave: Last SCLK edge to SS n negated (SS input
hold time)
CSPI master: CSPI1_RDY low to SS n asserted
(CSPI1_RDY setup time)
CSPI master: SS n negated to CSPI1_RDY low
Output data setup time
Output data hold time
Input data setup time
Input data hold time
Pause between data word
External Memory Interface (EMI) Timing
Parameter Description
i.MX25 Applications Processor for Automotive Products, Rev. 9
Table 43. CSPI Interface Timing Parameters
Symbol
t
t
t
t
t
t
t
Sdatao
Hdatao
t
t
t
t
t
Sdatai
Hdatai
t
t
t
t
pause
clkoH
Wsso
t
t
clkoL
clkiH
Wssi
Ssso
Hsso
t
t
Srdy
Hrdy
clkiL
Sssi
Hssi
clko
clki
pr
1
(t
t
2T
t
clkoL
clkoL
clkiL
t
clkiL
Minimum
sclk
T
ipg
22.65
22.47
3T
2T
2T
T
or t
T
or t
60.2
60.2
30.1
30.1
or t
T
2.6
2
30
per
or t
ipg
per
0
0
0
+ 0.5
sclk
sclk
+T
per
clkiH
clkoH
clkoH
5
4
clkiH
wait
) –
or
3
or
Maximum
5T
8.5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
per
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
—
—
—
—
—
—
—
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