MCIMX255AJM4AR2 Freescale Semiconductor, MCIMX255AJM4AR2 Datasheet - Page 40

• Manufacturer Part Number: MCIMX255AJM4AR2
• Description: Processors - Application Specialized IMX25 1.2 AUTO
• Manufacturer: Freescale Semiconductor

Specifications of MCIMX255AJM4AR2

• Core: ARM926EJ-S
• Processor Series: MCIMX25
• Maximum Clock Frequency: 400 MHz
• Instruction / Data Cache Memory: 16 KB
• Data Ram Size: 128 KB
• Operating Supply Voltage: 1.15 V to 1.52 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: MAPBGA-400
• Interface Type: USB
• Memory Type: DDR2
• Minimum Operating Temperature: - 40 C

1
2
3
4
Table 31
40
Output pad propagation delay
signals and crossing of output signals
Output enable to output valid delay, 50%–50%
Output enable to output valid delay, 40%–60%
Output pad slew rate
Output pad dI/dt
Input pad transition times
Input pad propagation delay, 50%–50%
Input pad propagation delay, 40%–60%
1
2
3
4
AC input logic high
AC input logic low
AC differential input voltage
AC differential cross point voltage for input
AC differential cross point voltage for output
Maximum condition for tpr, tpo, tpi, and tpv: wcs model, 1.1 V, I/O 1. V, and 105 °C. Minimum condition for tpr, tpo, and tpv: bcs
model, 1.3 V, I/O 1.9 V and –40 °C. Input transition time from core is 1 ns (20%–80%).
Minimum condition for tps: wcs model, 1.1 V, I/O 1.7 V, and 105 °C. tps is measured between VIL to VIH for rising edge and
between VIH to VIL for falling edge.
Maximum condition for tdit: bcs model, 1.3 V, I/O 1.9 V, and –40 °C.
Maximum condition for tpi and trfi: wcs model, 1.1 V, I/O 1.7 V and 105 °C. Minimum condition for tpi and trfi: bcs model, 1.3 V,
I/O 1.9 V and –40 °C. Input transition time from pad is 5 ns (20%–80%).
The Jedec SSTL_18 specification (JESD8-15a) for an SSTL interface for class II operation supersedes any specification in
this document.
Vid(ac) specifies the input differential voltage |Vtr–Vcp| required for switching, where Vtr is the “true” input signal and Vcp is
the “complementary” input signal. The minimum value is equal to Vih(ac)–Vil(ac)
The typical value of Vix(ac) is expected to be about 0.5
indicates the voltage at which differential input signal must cross.
The typical value of Vox(ac) is expected to be about 0.5
indicates the voltage at which differential output signal must cross. Cload = 25 pF.
shows the AC requirements for DDR2 I/O.
3
Parameter
Table 30. AC Parameters for DDR2 pbijtov18_33_ddr_clk I/O (continued)
Parameter
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4
2
i.MX25 Applications Processor for Automotive Products, Rev. 9
1
, 40%–60% input
1
Table 31. AC Requirements for DDR2 I/O
4
4
3
4
1
1
Symbol
Symbol
tpo
VIH(ac)
Vox(ac)
tpv
tpv
tps
tdit
VIL(ac)
trfi
Vid(ac)
Vix(ac)
tpi
tpi
OVDD. and Vix(ac) is expected to track variation of OVDD. Vix(ac)
OVDD and Vox(ac) is expected to track variation in OVDD. Vox(ac)
Condition
1.0 pF
1.0 pF
1.0 pF
25 pF
50 pF
25 pF
50 pF
25 pF
50 pF
25 pF
50 pF
25 pF
50 pF
Load
OVDD/2 + 0.25
OVDD/2–0.175
OVDD/2–0.125
Min.
–0.3
0.5
1.47/1.38
1.75/1.67
1.32/1.28
1.66/1.65
1.40/1.37
1.67/1.66
0.86/0.98
0.07/0.08
0.89/0.87
1.71/1.69
Rise/Fall
0.46/054
Min.
72
77
2.13/2.00
2.54/2.40
2.11/2.00
2.61/2.50
2.16/2.06
2.56/2.45
0.72/0.81
0.10/0.12
1.41/1.37
2.22/2.18
OVDD/2 + 0.175
OVDD/2 + 0.125
1.35/1.5
OVDD/2 – 0.25
Typ.
OVDD + 0.3
OVDD + 0.6
172
183
Max.
Freescale Semiconductor
3.072/2.87
3.65/3.45
3.31/3.12
4.06/3.81
3.30/3.13
3.89/3.67
2.15/2.19
1.12/1.16
0.17/0.20
2.16/2.07
2.98/2.88
Rise/Fall
Max.
400
422
Units
mA/ns
Units
V
V
V
V
V
V/ns
ns
ns
ns
ns
ns
ns