XRT83SL38ES Exar, XRT83SL38ES Datasheet - Page 84

• Manufacturer Part Number: XRT83SL38ES
• Description: Peripheral Drivers & Components - PCIs 8 CHT1/E1LIUSH
• Manufacturer: Exar

Specifications of XRT83SL38ES

• Product Category: Peripheral Drivers & Components - PCIs
• Rohs: yes

XRT83SL38
OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
MICROPROCESSOR INTERFACE I/O TIMING
I
The signals used for the Intel microprocessor interface are: Address Latch Enable (ALE), Read Enable (RD),
Write Enable (WR), Chip Select (CS), Address and Data bits. The microprocessor interface uses minimum ex-
ternal glue logic and is compatible with the timings of the 8051 or 80C188 with an 8-16 MHz clock frequency,
and with the timings of x86 or i960 family or microprocessors. The interface timing shown in
Figure 29
F
Reset pulse width - both Motorola and Intel Operations (see
NTEL
IGURE
R DY _D TAC K
AD D R[6:0]
DA TA[7:0]
W R _R/W
ALE_AS
I
R D _D S
S
NTERFACE
27. I
YMBOL
NA
NA
C S
t
t
t
t
t
t
t
0
1
2
3
4
5
9
is described in
NTEL
T
T
ABLE
t
A
0
IMING
SYNCHRONOUS
t
Valid Address to CS Falling Edge
CS Falling Edge to RD Assert
RD Assert to RDY Assert
RD Pulse Width (t2)
CS Falling Edge to WR Assert
WR Assert to RDY Assert
WR Pulse Width (t2)
CS Falling Edge to AS Falling Edge
Reset pulse width
5
51: A
t
1
- A
Table
SYNCHRONOUS
SYNCHRONOUS
R EAD OPER ATIO N
Valid Address
51.
t
2
P
P
ROGRAMMED
ARAMETER
V alid Data for R eadback
M
ODE
I/O I
1 - I
NTERFACE
NTEL
82
Figure 29
8051
T
t
0
AND
IMING
t
5
M
135
135
20
20
10
0
0
)
-
-
IN
80188 I
t
3
NTERFACE
D ata Available to W rite Into the LIU
W RITE OPER ATIO N
V alid Address
t
4
M
135
135
AX
-
-
-
-
-
-
T
IMING
Figure 27
U
REV. 1.0.2
NITS
µs
ns
ns
ns
ns
ns
ns
ns
ns
and