XRT83SL38ES Exar, XRT83SL38ES Datasheet - Page 61
XRT83SL38ES
Manufacturer Part Number
XRT83SL38ES
Description
Peripheral Drivers & Components - PCIs 8 CHT1/E1LIUSH
Manufacturer
Exar
Datasheet
1.XRT83SL38ES.pdf
(88 pages)
Specifications of XRT83SL38ES
Product Category
Peripheral Drivers & Components - PCIs
Rohs
yes
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REV. 1.0.2
R
EGISTER
00000101
00010101
00100101
00110101
01000101
01010101
01100101
01110101
B
D7
D6
D5
D4
IT
A
#
DDRESS
OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
C
C
C
C
C
C
C
C
C
Reserved
HANNEL
HANNEL
HANNEL
HANNEL
HANNEL
HANNEL
HANNEL
HANNEL
HANNEL
DMO_n
LCV_n
FLS_n
N
AME
T
ABLE
_n
_0
_1
_2
_3
_4
_5
_6
_7
24: M
Driver Monitor Output: This bit is set to a “1” to indicate
transmit driver failure is detected. The value of this bit is based
on the current status of DMO for the corresponding channel. If
the DMOIE bit is enabled, any transition on this bit will gener-
ate an Interrupt.
FIFO Limit Status: This bit is set to a “1” to indicate that the jit-
ter attenuator read/write FIFO pointers are within +/- 3 bits. If
the FLSIE bit is enabled, any transition on this bit will generate
an Interrupt.
Line Code Violation: This bit is set to a “1” to indicate that the
receiver of channel n is currently detecting a Line Code Viola-
tion or an excessive number of zeros in the B8ZS or HDB3
modes. If the LCVIE bit is enabled, any transition on this bit will
generate an Interrupt.
ICROPROCESSOR
59
R
EGISTER
F
UNCTION
#5, B
IT
D
ESCRIPTION
R
EGISTER
T
XRT83SL38
RO
RO
RO
RO
YPE
R
V
ALUE
ESET
0
0
0
0
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