XRT83SL38ES Exar, XRT83SL38ES Datasheet - Page 28

• Manufacturer Part Number: XRT83SL38ES
• Description: Peripheral Drivers & Components - PCIs 8 CHT1/E1LIUSH
• Manufacturer: Exar

Specifications of XRT83SL38ES

• Product Category: Peripheral Drivers & Components - PCIs
• Rohs: yes

F
XRT83SL38
OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
Once the T1/E1 input signal has been normalized to 0dB by adding the maximum gain (+29dB), the receiver
will declare RLOS if the signal is attenuated by an additional -9dB. The total cable loss at RLOS declaration is
typically -38dB (-29dB + -9dB). A 3dB hysteresis was designed so that transients will not trigger the RLOS to
clear. Therefore, the RLOS will typically clear at a total flat loss of -35dB. See
RECEIVE HDB3/B8ZS DECODER
The Decoder function is available in both Hardware and Host modes on a per channel basis by controlling the
TNEG_n/CODES_n pin or the CODES_n interface bit. The decoder function is only active in single-rail Mode.
When selected, receive data in this mode will be decoded according to HDB3 rules for E1 and B8ZS for T1
systems. Bipolar violations that do not conform to the coding scheme will be reported as Line Code Violation at
the RNEG_n/LCV_n pin of each channel. The length of the LCV pulse is one RCLK cycle for each code
violation. In E1mode only, an excessive number of zeros in the receive data stream is also reported as an error
at the same output pin. If AMI decoding is selected in single rail mode, every bipolar violation in the receive
data stream will be reported as an error at the RNEG_n/LCV_n pin.
RECOVERED CLOCK (RCLK) SAMPLING EDGE
This feature is available in both Hardware and Host modes on a global basis. In Host mode, the sampling
edge of RCLK output can be changed through the interface control bit RCLKE. If a “1” is written in the RCLKE
interface bit, receive data output at RPOS_n/RDATA_n and RNEG_n/LCV_n are updated on the falling edge of
RCLK for all eight channels. Writing a “0” to the RCLKE register, updates the receive data on the rising edge of
RCLK. In Hardware mode the same feature is available under the control of the RCLKE pin.
F
IGURE
IGURE
RCLK
RNEG
RPOS
6. S
7. R
or
IMPLIFIED
ECEIVE
+3dB
C
LOCK AND
D
IAGRAM OF
-9dB
O
R
UTPUT
-29dB T1/E1 G
DY
D
ATA
+3dB
T
IMING
AIN
M
26
ODE AND
-9dB
R
HO
RCLK
RLOS C
Clear LOS
Declare LOS
Declare LOS
Clear LOS
Normalized up to +29dB Max
Normalized up to +29dB Max
R
ONDITION
Figure 6
RCLK
F
for a simplified diagram.
REV. 1.0.2