XRT83SL38ES Exar, XRT83SL38ES Datasheet - Page 8

• Manufacturer Part Number: XRT83SL38ES
• Description: Peripheral Drivers & Components - PCIs 8 CHT1/E1LIUSH
• Manufacturer: Exar

Specifications of XRT83SL38ES

• Product Category: Peripheral Drivers & Components - PCIs
• Rohs: yes

XRT83SL38
OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
PIN DESCRIPTION BY FUNCTION
RECEIVE SECTIONS
S
IGNAL
RNEG_0
RNEG_1
RNEG_2
RNEG_3
RNEG_4
RNEG_5
RNEG_6
RNEG_7
RLOS_0
RLOS_1
RLOS_2
RLOS_3
RLOS_4
RLOS_5
RLOS_6
RLOS_7
RCLK_0
RCLK_1
RCLK_2
RCLK_3
RCLK_4
RCLK_5
RCLK_6
RCLK_7
LCV_0
LCV_1
LCV_2
LCV_3
LCV_4
LCV_5
LCV_6
LCV_7
N
AME
L
EAD
H15
H16
M15
U16
H18
M16
A16
T15
A17
B16
V17
J15
M4
C3
H4
H3
U3
H2
V3
L2
B3
L3
A2
A2
T4
#
T
YPE
O
O
O
Receiver Loss of Signal for Channel_ 0:
This output signal goes “High” for at least one RCLK_0 cycle to indicate loss of signal
at the receive 0 input. RLOS will remain “High” for the entire duration of the Loss of Sig-
nal detected by the receiver logic.
SEE”RECEIVER LOSS OF SIGNAL (RLOS)” ON PAGE 25.
Receiver Loss of Signal for Channel _1
Receiver Loss of Signal for Channel _2
Receiver Loss of Signal for Channel _3
Receiver Loss of Signal for Channel _4
Receiver Loss of Signal for Channel_ 5
Receiver Loss of Signal for Channel _6
Receiver Loss of Signal for Channel _7
Receiver Clock Output for Channel _0
Receiver Clock Output for Channel _1
Receiver Clock Output for Channel _2
Receiver Clock Output for Channel _3
Receiver Clock Output for Channel _4
Receiver Clock Output for Channel _5
Receiver Clock Output for Channel _6
Receiver Clock Output for Channel _7
Receiver Negative Data Output for Channel_0 - Dual-Rail mode
This signal is the receive negative-rail output data.
Line Code Violation Output for Channel_0 - Single-Rail mode
This signal goes “High” for one RCLK_0 cycle to indicate a code violation is detected in
the received data of Channel _0. If AMI coding is selected, every bipolar violation
received will cause this pin to go “High”.
Receiver Negative Data Output for Channel _1
Line Code Violation Output for Channel _1
Receiver Negative Data Output for Channel _2
Line Code Violation Output for Channel _2
Receiver Negative Data Output for Channel _3
Line Code Violation Output for Channel _3
Receiver Negative Data Output for Channel _4
Line Code Violation Output for Channel _4
Receiver Negative Data Output for Channel _5
Line Code Violation Output for Channel _5
Receiver Negative Data Output for Channel _6
Line Code Violation Output for Channel _6
Receiver Negative Data Output for Channel _7
Line Code Violation Output for Channel _7
6
D
ESCRIPTION
REV. 1.0.2