XRT83SL38ES Exar, XRT83SL38ES Datasheet - Page 46
XRT83SL38ES
Manufacturer Part Number
XRT83SL38ES
Description
Peripheral Drivers & Components - PCIs 8 CHT1/E1LIUSH
Manufacturer
Exar
Datasheet
1.XRT83SL38ES.pdf
(88 pages)
Specifications of XRT83SL38ES
Product Category
Peripheral Drivers & Components - PCIs
Rohs
yes
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XRT83SL38
OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
In the Remote Loop-Back mode if the jitter attenuator is selected in the transmit path, the receive data from the
Clock and Data Recovery block is looped back to the transmit path and is applied to the jitter attenuator using
RCLK as transmit timing. In this mode the transmit clock and data are also ignored, while RCLK and received
data will continue to be available at their respective output pins. Remote Loop-Back with the jitter attenuator
selected in the transmit path is shown in
DIGITAL LOOP-BACK (DLOOP)
Digital Loop-Back or Local Loop-Back allows the transmit clock and data to be looped back to the
corresponding receiver output pins through the encoder/decoder and jitter attenuator. In this mode, receive
data and clock are ignored, but the transmit data will be sent to the line uninterrupted. This loop back feature
allows users to configure the line interface as a pure jitter attenuator. The Digital Loop-Back signal flow is
shown in
Figure 20.
F
F
IGURE
IGURE
RPOS
RNEG
TNEG
TPOS
RCLK
TCLK
RNEG
TNEG
RPOS
TPOS
RCLK
TCLK
19. R
20. D
EMOTE
IGITAL
Encoder
Decoder
Encoder
Decoder
L
L
OOP
OOP
-
-
Figure
BACK MODE WITH JITTER ATTENUATOR SELECTED IN
BACK MODE WITH JITTER ATTENUATOR SELECTED IN
JA
19.
JA
44
Timing
Control
Recovery
Data &
Clock
Timing
Control
Recovery
Clock &
Data
Tx
Tx
Rx
Rx
TTIP
TRING
RTIP
RRING
TTIP
TRING
RTIP
RRING
T
T
RANSMIT PATH
RANSMIT PATH
REV. 1.0.2
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