XRT83SL38ES Exar, XRT83SL38ES Datasheet - Page 47
![no-image](/images/no-image-200.jpg)
XRT83SL38ES
Manufacturer Part Number
XRT83SL38ES
Description
Peripheral Drivers & Components - PCIs 8 CHT1/E1LIUSH
Manufacturer
Exar
Datasheet
1.XRT83SL38ES.pdf
(88 pages)
Specifications of XRT83SL38ES
Product Category
Peripheral Drivers & Components - PCIs
Rohs
yes
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REV. 1.0.2
DUAL LOOP-BACK
Figure 21
path will have the same result as placing the jitter attenuator in the receive path. In dual Loop-Back mode the
recovered clock and data from the line are looped back through the transmitter to the TTIP and TRING without
passing through the jitter attenuator. The transmit clock and data are looped back through the jitter attenuator
to the RCLK and RPOS/RDATA and RNEG pins.
depicts the data flow in dual-loopback. In this mode, selecting the jitter attenuator in the transmit
F
IGURE
OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
21. S
RPOS
RNEG
TNEG
TPOS
RCLK
TCLK
IGNAL FLOW IN
Encoder
Decoder
D
UAL LOOP
JA
-
BACK MODE
45
Timing
Control
Recovery
Data &
Clock
Tx
Rx
TTIP
TRING
RTIP
RRING
XRT83SL38
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