XRT83SL38ES Exar, XRT83SL38ES Datasheet - Page 17

• Manufacturer Part Number: XRT83SL38ES
• Description: Peripheral Drivers & Components - PCIs 8 CHT1/E1LIUSH
• Manufacturer: Exar

Specifications of XRT83SL38ES

• Product Category: Peripheral Drivers & Components - PCIs
• Rohs: yes

REV. 1.0.2
JITTER ATTENUATOR
CLOCK SYNTHESIZER
MCLKOUT
JASEL0
JASEL1
S
MCLKT1
MCLKE1
N
S
IGNAL
N
AME
IGNAL
AME
L
OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
EAD
A14
B13
L
EAD
H1
K1
J1
#
#
T
YPE
T
I
YPE
O
I
I
Jitter Attenuator Select Pins Hardware Mode
Jitter Attenuator select Bit 0
Jitter Attenuator select Bit 1
JASEL[1:0] pins are used to place the jitter attenuator in the transmit path, the receive
path or to disable it.
N
Synthesized Master Clock Output
This signal is the output of the Master Clock Synthesizer PLL which is at T1 or E1 rate
based upon the mode of operation.
T1 Master Clock Input
This signal is an independent 1.544MHz clock for T1 systems with accuracy better than
±50ppm and duty cycle within 40% to 60%. MCLKT1 is used in the T1 mode.
N
E1 Master Clock Input
A 2.048MHz clock for with an accuracy of better than ±50ppm and a duty cycle of 40%
to 60% can be provided at this pin.
In systems that have only one master clock source available (E1 or T1), that clock
should be connected to both MCLKE1 and MCLKT1 inputs for proper operation.
N
OTE
OTES
OTES
: These pins are internally pulled “Low” with 50kΩ resistors.
JASEL1
1. All channels of the XRT83L38 must be operated at the same clock rate, either
2. See pin 26 description for further explanation for the usage of this pin.
3. Internally pulled “Low” with a 50kΩ resistor.
1. All channels of the XRT83L38 must be operated at the same clock rate, either
2. Internally pulled “Low” with a 50kΩ resistor.
:
:
0
0
1
1
T1, E1 or J1.
T1, E1 or J1.
JASEL0
0
1
0
1
15
Disabled
Transmit
JA Path
Receive
Receive
D
D
ESCRIPTION
ESCRIPTION
-----
T1
JA BW Hz
3
3
3
-----
1.5
E1
10
10
FIFO Size
--------
32/32
32/32
64/64
XRT83SL38