XRT83SL38ES Exar, XRT83SL38ES Datasheet - Page 6

• Manufacturer Part Number: XRT83SL38ES
• Description: Peripheral Drivers & Components - PCIs 8 CHT1/E1LIUSH
• Manufacturer: Exar

Specifications of XRT83SL38ES

• Product Category: Peripheral Drivers & Components - PCIs
• Rohs: yes

XRT83SL38
OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
MICROPROCESSOR PARALLEL INTERFACE .............................................................. 46
TRANSMITTER (C
REDUNDANCY APPLICATIONS ............................................................................................................. 35
TYPICAL REDUNDANCY SCHEMES ..................................................................................................... 36
P
T
N
T
L
L
R
D
D
M
M
OOP
OCAL
RANSMIT
RANSMIT AND
ATTERN
ETWORK
EMOTE
IGITAL
UAL
ICROPROCESSOR
ICROPROCESSOR
Figure 12. Simplified Diagram for E1 in External Termination Mode (RXTSEL= 0) ................... 34
Transmit Termination Mode .................................................................................................................................. 34
T
T
External Transmit Termination Mode ................................................................................................................... 34
T
T
Figure 13. Simplified Block Diagram of the Transmit Section for 1:1 & 1+1 Redundancy ....... 37
Figure 14. Simplified Block Diagram - Receive Section for 1:1 and 1+1 Redundancy .............. 37
Figure 15. Simplified Block Diagram - Transmit Section for N+1 Redundancy ......................... 38
Figure 16. Simplified Block Diagram - Receive Section for N+1 Redundancy ........................... 39
T
T
T
T
Figure 17. Local Analog Loop-back signal flow ............................................................................ 43
Figure 18. Remote Loop-back mode with jitter attenuator selected in receive path ................. 43
Figure 19. Remote Loop-back mode with jitter attenuator selected in Transmit path .............. 44
Figure 20. Digital Loop-back mode with jitter attenuator selected in Transmit path ................ 44
Figure 21. Signal flow in Dual loop-back mode ............................................................................. 45
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
-B
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
L
A
OOP
ACK
L
NALOG
L
OOP
T
OOP
A
L
RANSMIT AND
8: T
9: T
10: T
11: T
12: P
13: L
14: L
15: L
16: M
17: M
18: M
19: M
20: M
21: M
22: M
23: M
24: M
25: M
26: M
27: M
28: M
29: M
30: M
31: M
32: M
33: M
34: M
35: M
-B
OOP
LL
M
-B
ACK
ODES
-B
O
D
RANSMIT
ERMINATION
L
ACK
NES
C
RANSMIT
RANSMIT
OOP
ETECT
OOP
OOP
ACK
ATTERN TRANSMISSION CONTROL
OOP
ICROPROCESSOR INTERFACE SIGNAL DESCRIPTION
ICROPROCESSOR
ICROPROCESSOR
ICROPROCESSOR
ICROPROCESSOR
ICROPROCESSOR
ICROPROCESSOR
ICROPROCESSOR
ICROPROCESSOR
ICROPROCESSOR
ICROPROCESSOR
ICROPROCESSOR
ICROPROCESSOR
ICROPROCESSOR
ICROPROCESSOR
ICROPROCESSOR
ICROPROCESSOR
ICROPROCESSOR
ICROPROCESSOR
ICROPROCESSOR
ODE
...................................................................................................................................... 45
R
R
HANNELS
.................................................................................................................................... 42
(DLOOP) ................................................................................................................... 44
EGISTER
EGISTER
-C
-
-
(TAOS) ..................................................................................................................... 40
-B
(RLOOP) .................................................................................................................. 43
BACK CONTROL IN
BACK CONTROL IN
D
ODE
Q
ACK
T
D
ETECTION AND
UASI
ERMINATION
T
T
ETECT
ERMINATION
ERMINATIONS
S
D
(ALOOP) ........................................................................................................ 43
0 - 7) ............................................................................................................ 34
ELECT
ETECTION
-R
T
D
ABLES
ESCRIPTIONS
ANDOM
F
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
UNCTION
C
EGISTER
EGISTER
EGISTER
EGISTER
EGISTER
EGISTER
EGISTER
EGISTER
EGISTER
EGISTER
EGISTER
EGISTER
EGISTER
EGISTER
EGISTER
EGISTER
EGISTER
EGISTER
EGISTER
ONTROL
........................................................................................................ 47
C
T
S
C
C
H
H
ONTROL
RANSMISSION
IGNAL
ONTROL
................................................................................................... 35
ONTROL
ARDWARE MODE
OST MODE
............................................................................................... 40
.............................................................................................. 51
A
B
#0, B
#1, B
#2, B
#3, B
#4, B
#5, B
#6, B
#7, B
#8, B
#9, B
#10, B
#11, B
#12, B
#13, B
#14, B
#15, B
#128, B
........................................................................................... 34
DDRESS
IT
S
OURCE
D
....................................................................................... 34
...................................................................................... 40
..................................................................................... 35
..................................................................................... 40
IT
IT
IT
IT
IT
IT
IT
IT
IT
IT
ESCRIPTION
II
IT
IT
IT
IT
IT
IT
.................................................................................. 42
D
D
D
D
D
D
D
D
D
D
IT
D
D
D
D
D
D
............................................................................... 40
ESCRIPTION
ESCRIPTION
ESCRIPTION
ESCRIPTION
ESCRIPTION
ESCRIPTION
ESCRIPTION
ESCRIPTION
ESCRIPTION
ESCRIPTION
D
............................................................................. 47
ESCRIPTION
ESCRIPTION
ESCRIPTION
ESCRIPTION
ESCRIPTION
ESCRIPTION
(TDQRSS) ......................................................... 41
ESCRIPTION
........................................................................ 42
.................................................................. 47
............................................................ 51
............................................................ 52
............................................................ 54
............................................................ 56
............................................................ 58
............................................................ 59
............................................................ 61
............................................................ 62
............................................................ 63
............................................................ 63
........................................................... 46
.......................................................... 64
.......................................................... 64
.......................................................... 65
.......................................................... 65
.......................................................... 66
.......................................................... 66
........................................................ 67
REV. 1.0.2