XRT83SL38ES Exar, XRT83SL38ES Datasheet

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... FAX (510) 668-7017 XRT83SL38 REV. 1.0.2 ) ODE MCLKOUT DRIVE DMO_n DFM MONITOR TTIP_n TX FILTER LINE & PULSE DRIVER SHAPER TRING_n LBO[3:0] TXON_n LOCAL ANALOG LOOPBACK PEAK RTIP_n RX DETECTOR EQUALIZER RRING_n & SLICER ICT TEST μPTS1 μPTS2 D[7:0] μPCLK A[7:0] RESET • www.exar.com ...

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XRT83SL38 OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR IGURE LOCK IAGRAM OF THE MCLKE1 MCLKT1 MASTER CLOCK SYNTHESIZER CLKSEL[2:0] One of Eight Channels, CHANNEL_n - (n TPOS_n/TDATA_n QRSS HDB3/ TNEG_n/CODES_n PATTERN ...

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OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.2 • Error and Bipolar Violation Insertion and Detection • Receiver Line Attenuation Indication Output in 1dB steps • Network Loop-Code Detection for automatic Loop-Back Activation/Deactivation • Transmit All ...

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XRT83SL38 OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR 4 REV. 1.0.2 ...

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OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.2 GENERAL DESCRIPTION .................................................................................................. 1 A .............................................................................................................................................. 1 PPLICATIONS Figure 1. Block Diagram of the XRT83SL38 T1/E1/J1 LIU (Host Mode) ........................................ 1 Figure 2. Block Diagram of the XRT83SL38 ...

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XRT83SL38 OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR Figure 12. Simplified Diagram for E1 in External Termination Mode (RXTSEL= 0) ................... 34 TRANSMITTER ( ............................................................................................................ 34 HANNELS Transmit Termination Mode .................................................................................................................................. ...

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OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.2 CLOCK SELECT REGISTER ............................................................................................ 68 Figure 22. Register 0x81h Sub Registers ...................................................................................... 68 T 36: M ABLE ICROPROCESSOR T 37: M ABLE ICROPROCESSOR T 38: M ABLE ICROPROCESSOR ...

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XRT83SL38 OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR PIN DESCRIPTION BY FUNCTION RECEIVE SECTIONS IGNAL AME EAD YPE RLOS_0 C3 O Receiver Loss of Signal for Channel_ 0: This output signal goes ...

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OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0 IGNAL AME EAD YPE RPOS_0 B2 O Receiver Positive Data Output for Channel _0 - Dual-Rail mode This signal is the receive positive-rail ...

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XRT83SL38 OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR IGNAL AME EAD YPE Receive External Resistor Control Pins - Hardware mode RXRES1 R10 I Receive External Resistor Control Pin 1: RXRES0 V10 Receive ...

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OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0 IGNAL AME EAD YPE TRING_0 E2 O Transmitter Ring Output for Channel _0 Negative differential transmit output to the line. TRING_1 F3 Transmitter ...

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XRT83SL38 OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR IGNAL AME EAD YPE TNEG_0 C4 I Transmitter Negative NRZ Data Input for Channel _0 Dual-Rail mode This signal is the negative-rail input data ...

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OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0 IGNAL AME EAD YPE TAOS_0 D6 I Transmit All Ones for Channel _0 - Hardware mode Setting this pin “High” enables the transmission ...

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XRT83SL38 OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR MICROPROCESSOR INTERFACE IGNAL AME EAD YPE HW_HOST T10 I Mode Control Input This pin selects Hardware or Host mode. Leave this pin unconnected or ...

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OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0 IGNAL AME EAD YPE RDY_DTACK A6 O Ready Output (Data Transfer Acknowledge Output) - Host mode Intel bus timing: RDY is asserted “High” ...

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XRT83SL38 OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR IGNAL AME EAD YPE Microprocessor Interface Address Bus Pins - Host mode: A[7] A12 I Microprocessor Interface Address Bus[7] A[6] B11 Microprocessor Interface Address ...

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OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.2 JITTER ATTENUATOR S IGNAL EAD YPE N AME Jitter Attenuator Select Pins Hardware Mode JASEL0 A14 I Jitter Attenuator select Bit 0 JASEL1 B13 Jitter ...

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XRT83SL38 OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR S IGNAL EAD YPE N AME CLKSEL0 A8 I Clock Select inputs for Master Clock Synthesizer - Hardware mode CLKSEL1 B8 CLKSEL[2:0] are input signals to ...

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... N OTE RESET T8 I Hardware Reset (Active “Low”): When this pin is tied “Low” for more than 10µs, the device is put in the reset state. Exar recommends initiating a Hardware reset upon power up. N OTE SR/ Single-Rail/Dual-Rail Data Format: Connect this pin “Low” to select transmit and receive data format in Dual-Rail mode. In this mode, HDB3 or B8ZS encoder and decoder are not available. Connect this pin “ ...

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XRT83SL38 OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR IGNAL AME EAD YPE Loop-back Control Pins, Bits [1:0] Channel_[7:0] LOOP1_0 A10 I Loop-back Control bit 1, Channel _0 LOOP0_0 C10 Loop-back Control bit ...

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OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0 IGNAL AME EAD YPE EQC4 A6 I Equalizer Control Input 4 - Hardware mode This pin together with pins EQC[3:0] is used to ...

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XRT83SL38 OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR IGNAL AME EAD YPE TERSEL1 T11 I Termination Impedance Select bit 1: TERSEL0 R11 Termination Impedance Select bit 0: In the Hardware mode and ...

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OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0 IGNAL AME EAD YPE TVDD_0 E4 **** TVDD_1 F4 TVDD_2 F16 TVDD_3 E17 TVDD_4 R4 TVDD_5 P1 TVDD_6 N15 TVDD_7 P15 RVDD_0 C2 ...

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XRT83SL38 OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR PINS ONLY AVAILABLE IN BGA PACKAGE IGNAL AME EAD YPE DVDD_DRV J4 **** DVDD_DRV D9 DGND_DRV G15 **** DGND_DRV K2 RXON K16 I NC1 ...

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OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.2 FUNCTIONAL DESCRIPTION The XRT83SL38 is a fully integrated short-haul transceiver intended for T1 systems. Simplified block diagrams of the chip are shown in Figure In ...

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XRT83SL38 OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR MCLKE1 MCLKT1 CLKSEL2 2048 2048 2048 2048 2048 1544 1544 1544 1544 1544 2048 1544 ...

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OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.2 RECEIVE MONITOR MODE In applications where Monitor mode is desired, the equalizer can be configured in a gain mode which handles input signals attenuated resistively up to 29dB, ...

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XRT83SL38 OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR Once the T1/E1 input signal has been normalized to 0dB by adding the maximum gain (+29dB), the receiver will declare RLOS if the signal is attenuated by an additional ...

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OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.2 JITTER ATTENUATOR To reduce phase and frequency jitter in the recovered clock, the jitter attenuator can be placed in the receive signal path. The jitter attenuator uses a ...

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XRT83SL38 OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR ARBITRARY PULSE GENERATOR FOR T1 AND E1 The arbitrary pulse generator divides the pulse into eight individual segments. Each segment is set by a 7-Bit binary word by programming ...

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OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0 IGURE RANSMIT LOCK AND NPUT TCLK TPOS/TDATA or TNEG T SU TRANSMIT HDB3/B8ZS ENCODER The Encoder function is available in both Hardware and ...

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XRT83SL38 OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR The driver monitor circuit is used to detect transmit driver failure by monitoring the activities at TTIP and TRING outputs. Driver failure may be caused by a short circuit ...

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OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0 ABLE ECEIVE QUALIZER EQC4 EQC3 EQC2 EQC1 TRANSMIT AND RECEIVE TERMINATIONS The XRT83SL38 is a versatile ...

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XRT83SL38 OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR If the internal termination mode (RXTSEL = “1”) is selected, the effective impedance for E1 can be achieved either with an internal resistor or a combination ...

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OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.2 RXTSEL TERSEL1 TERSEL0 ...

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XRT83SL38 OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR F 12. S IGURE IMPLIFIED ...

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OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.2 diagram for T1 (100Ω) in the external termination mode. the external termination mode. T ABLE Table 11 summarizes the transmit terminations. TERSEL1 TERSEL0 ...

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XRT83SL38 OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR PROGRAMMING CONSIDERATIONS In many applications switching the control of the transmitter outputs and the receiver line impedance to hardware control will provide faster transmitter ON/OFF switching. In Host Mode, ...

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OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0 IGURE IMPLIFIED LOCK Backplane Interface Primary Card TxTSEL=1, Internal Backup Card TxTSEL=1, Internal RECEIVE 1:1 & 1+1 REDUNDANCY For 1:1 and 1+1 redundancy, the ...

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XRT83SL38 OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR N+1 redundancy has one backup card for N primary cards. Due to impedance mismatch and signal contention, external relays are necessary when using this redundancy scheme. The advantage of ...

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OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.2 RECEIVE For N+1 redundancy, the receivers on the primary cards should be programmed for internal impedance mode. The receivers on the backup card should be programmed for external ...

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XRT83SL38 OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR PATTERN TRANSMIT AND DETECT FUNCTION Several test and diagnostic patterns can be generated and detected by the chip. In Hardware mode each channel can be independently programmed to transmit ...

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OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.2 Network Loop-Up Code. In this mode if the NLCD interrupt is enabled, the chip will initiate an interrupt on every transition of NLCD. The host has the option ...

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XRT83SL38 OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR LOOP-BACK MODES The XRT83SL38 supports several Loop-Back modes under both Hardware and Host control. In Hardware mode the two LOOP[1:0] pins control the Loop-Back functions for each channel independently ...

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OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.2 LOCAL ANALOG LOOP-BACK (ALOOP) With Local Analog Loop-Back activated, the transmit data at TTIP and TRING are looped-back to the analog input of the receiver. External inputs at ...

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XRT83SL38 OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR In the Remote Loop-Back mode if the jitter attenuator is selected in the transmit path, the receive data from the Clock and Data Recovery block is looped back to ...

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OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.2 DUAL LOOP-BACK Figure 21 depicts the data flow in dual-loopback. In this mode, selecting the jitter attenuator in the transmit path will have the same result as placing ...

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XRT83SL38 OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR MICROPROCESSOR PARALLEL INTERFACE XRT83SL38 is equipped with a microprocessor interface for easy device configuration. The parallel port of the XRT83SL38 is compatible with both Intel and Motorola address and ...

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OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.2 MICROPROCESSOR REGISTER TABLES The microprocessor interface consists of 256 addressable locations. Each channel uses 16 dedicated 8 byte registers for independent programming and control. There are four additional ...

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XRT83SL38 OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR T 18: M ABLE DDRESS IT T YPE 4 00000100 R/W Reserved Hex 0x04 5 00000101 RO Reserved Hex ...

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OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.2 T 18: M ABLE DDRESS IT T YPE 128 10000000 R/W SR/DR Hex 0x80 129 10000001 R/W Reserved ...

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XRT83SL38 OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR T 18: M ABLE DDRESS IT T YPE 254 11111110 RO DEVICE ID hex: FC Binary : 11111100 Hex ...

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OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.2 MICROPROCESSOR REGISTER DESCRIPTIONS T 19: M ABLE EGISTER DDRESS HANNEL 00000000 C _0 HANNEL 00010000 C _1 HANNEL 00100000 C _2 HANNEL 00110000 C ...

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XRT83SL38 OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR T 20: M ABLE EGISTER DDRESS HANNEL 00000001 C _0 HANNEL 00010001 C _1 HANNEL 00100001 C _2 HANNEL 00110001 C _3 HANNEL 01000001 C ...

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OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.2 T 20: M ABLE D3 JASEL1_n Jitter Attenuator select bit 1: The JASEL1 and JASEL0 bits are used to disable or place the jitter attenuator of each chan- ...

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XRT83SL38 OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR T 21: M ABLE EGISTER DDRESS HANNEL 00000010 C _0 HANNEL 00010010 C _1 HANNEL 00100010 C _2 HANNEL 00110010 C _3 HANNEL 01000010 C ...

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OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.2 T 21: M ABLE D4 TXTEST0_n Transmit Test Pattern bit 0: See description of bit D6 for the function of this bit. D3 TXON_n Transmitter ON: Writing a ...

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XRT83SL38 OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR T 22: M ABLE EGISTER DDRESS HANNEL 00000011 C _0 HANNEL 00010011 C _1 HANNEL 00100011 C _2 HANNEL 00110011 C _3 HANNEL 01000011 C ...

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OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.2 T 22: M ABLE D4 RXRES1_n Receive External Resistor Control Pin 1: In Host mode, this bit along with the RXRES0_n bit selects the value of the exter- ...

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XRT83SL38 OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR T 23: M ABLE R A EGISTER DDRESS C _n HANNEL 00000100 C _0 HANNEL 00010100 C _1 HANNEL 00100100 C _2 HANNEL 00110100 C _3 HANNEL 01000100 C ...

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OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.2 T 24: M ABLE EGISTER DDRESS HANNEL 00000101 C _0 HANNEL 00010101 C _1 HANNEL 00100101 C _2 HANNEL 00110101 C _3 HANNEL 01000101 ...

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XRT83SL38 OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR T 24: M ABLE D3 NLCD_n Network Loop-Code Detection: This bit operates differently in the Manual or the Automatic Network Loop-Code detection modes. In the Manual Loop-Code detection mode, ...

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OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.2 T 25: M ABLE EGISTER DDRESS HANNEL 00000110 C _0 HANNEL 00010110 C _1 HANNEL 00100110 C _2 HANNEL 00110110 C _3 HANNEL 01000110 ...

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XRT83SL38 OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR T 26: M ABLE EGISTER DDRESS HANNEL 00000111 C _0 HANNEL 00010111 C _1 HANNEL 00100111 C _2 HANNEL 00110111 C _3 HANNEL 01000111 C ...

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OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.2 T 27: M ABLE EGISTER DDRESS HANNEL 00001000 C _0 HANNEL 00011000 C _1 HANNEL 00101000 C _2 HANNEL 00111000 C _3 HANNEL 01001000 ...

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XRT83SL38 OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR T 29: M ABLE EGISTER DDRESS HANNEL 00001010 C _0 HANNEL 00011010 C _1 HANNEL 00101010 C _2 HANNEL 00111010 C _3 HANNEL 01001010 C ...

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OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.2 T 31: M ABLE EGISTER DDRESS HANNEL 00001100 C _0 HANNEL 00011100 C _1 HANNEL 00101100 C _2 HANNEL 00111100 C _3 HANNEL 01001100 ...

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XRT83SL38 OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR T 33: M ABLE EGISTER DDRESS HANNEL 00001110 C _0 HANNEL 00011110 C _1 HANNEL 00101110 C _2 HANNEL 00111110 C _3 HANNEL 01001110 C ...

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OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.2 T 35: M ABLE R A EGISTER DDRESS 10000000 N AME SR/DR Single-rail/Dual-rail Select: Writing a “1” to this bit configures all 8 channels ...

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XRT83SL38 OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR CLOCK SELECT REGISTER The input clock source is used to generate all the necessary clock references internally to the LIU. The microprocessor timing is derived from a PLL output ...

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OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.2 T 36: M ABLE R A EGISTER DDRESS 10000001 N AME Reserved D6 CLKSEL2 Clock Select Inputs for Master Clock Synthesizer bit 2: In ...

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XRT83SL38 OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR T 36: M ABLE D1 EXLOS Extended LOS: Writing a “1” to this bit extends the number of zeros at the receive input of each channel before RLOS is ...

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OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.2 T 37: M ABLE D3 MONITOR_3 Protected Monitoring: With protected monitoring enabled, the receiver 7 inputs at RTIP_7 and RRING_7 are internally connected to one of the other ...

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XRT83SL38 OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR T 38: M ABLE R A EGISTER DDRESS 10000000 N AME GAUGE1 Wire Gauge Selector Bit 1: This bit together with bit D6 are used ...

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OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.2 T 39: M ABLE R A EGISTER DDRESS 11000000 N AME D[7:1] Reserved These register bits are not used. D0 E1Arben E1 Arbitrary Pulse Enable ...

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XRT83SL38 OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR ELECTRICAL CHARACTERISTICS Storage Temperature...................-65° 150°C Operating Temperature.............-40° 85°C Supply Voltage..........................- ABLE VDD=3.3V±5%, P ARAMETER Power Supply ...

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OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0 ABLE (VDD=3.3V±5%, P ARAMETER Receiver loss of signal: Number of consecutive zeros before RLOS is set Input signal level at RLOS RLOS De-asserted 12.5 ...

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XRT83SL38 OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR T 44 ABLE VDD=3.3V±5%, P ARAMETER Receiver loss of signal: Number of consecutive zeros before RLOS is set Input signal level at RLOS RLOS Clear Input Impedance ...

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OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0 ABLE VDD=3.3V±5%, P ARAMETER Output Pulse Width Ratio Output Pulse Amplitude Ratio Jitter Added by the Transmitter Out- put Output Return Loss: 51kHz -102kHz ...

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XRT83SL38 OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR F 23. ITU G.703 P IGURE V = 100% 50 ABLE Test Load Impedance Nominal Peak Voltage of a Mark Peak voltage of a Space (no Mark) ...

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OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.2 F 24. DSX IGURE ULSE EMPLATE T 49: DSX1 I ABLE M INIMUM CURVE T (UI) N IME ORMALIZED AMPLITUDE -0.77 -0.23 -0.23 -0.15 0.0 0.15 ...

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XRT83SL38 OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR T ABLE VDD=3.3V±5 ARAMETER E1 MCLK Clock Frequency T1 MCLK Clock Frequency MCLK Clock Duty Cycle MCLK Clock Tolerance TCLK Duty Cycle Transmit Data Setup Time Transmit ...

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OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0 IGURE ECEIVE LOCK AND UTPUT R DY RCLK RPOS or RNEG D T ATA IMING RCLK XRT83SL38 RCLK F ...

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XRT83SL38 OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR MICROPROCESSOR INTERFACE I/O TIMING NTEL NTERFACE IMING SYNCHRONOUS The signals used for the Intel microprocessor interface are: Address Latch Enable (ALE), Read Enable (RD), ...

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OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0 OTOROLA SYCHRONOUS NTERFACE The signals used in the Motorola microprocessor interface mode are: Address Strobe (AS), Data Strobe (DS), Read/Write Enable (R/W), Chip Select (CS), ...

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XRT83SL38 OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR PACKAGE DIMENSIONS 225 BALL PLASTIC BALL GRID ARRAY (BOTTOM VIEW) D Seating Plane Note: The control dim ension illimeter. SYMBO ...

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OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.0.2 ORDERING INFORMATION P N ART UMBER XRT83SL38IB P O ACKAGE PERATING 225 Ball BGA 85 XRT83SL38 T R EMPERATURE ANGE ° ° - +85 C ...

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... Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances ...