XRT83SL38ES Exar, XRT83SL38ES Datasheet - Page 72
![no-image](/images/no-image-200.jpg)
XRT83SL38ES
Manufacturer Part Number
XRT83SL38ES
Description
Peripheral Drivers & Components - PCIs 8 CHT1/E1LIUSH
Manufacturer
Exar
Datasheet
1.XRT83SL38ES.pdf
(88 pages)
Specifications of XRT83SL38ES
Product Category
Peripheral Drivers & Components - PCIs
Rohs
yes
- Current page: 72 of 88
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XRT83SL38
OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
R
EGISTER
10000010
D5-D4
B
D1
D0
D7
D6
IT
A
#
DDRESS
TXONCNTL Transmit On Control:
TERCNTL
EXLOS
N
T
ICT
T
AME
ABLE
ABLE
36: M
37: M
Extended LOS: Writing a “1” to this bit extends the number of
zeros at the receive input of each channel before RLOS is
declared to 4096 bits. Writing a “0” reverts to the normal mode
(175+75 bits for T1 and 32 bits for E1).
In-Circuit-Testing: Writing a “1” to this bit configures all the
output pins of the chip in high impedance mode for In-Circuit-
Testing. Setting the ICT bit to “1” is equivalent to connecting
the Hardware ICT pin 88 to ground.
In Host mode, setting this bit to “1” transfers the control of the
Transmit On/Off function to the TXON_n Hardware control
pins.
N
Termination Control.
In Host mode, setting this bit to “1” transfers the control of the
RXTSEL to the RXTSEL Hardware control pin.
N
OTE
OTE
ICROPROCESSOR
ICROPROCESSOR
: This provides a faster On/Off capability for redundancy
: This provides a faster On/Off capability for redundancy
application.
application.
R
R
70
EGISTER
EGISTER
F
UNCTION
Reserved
#129, B
#130, B
IT
IT
D
D
ESCRIPTION
ESCRIPTION
R
EGISTER
T
R/W
R/W
R/W
R/W
YPE
REV. 1.0.2
R
V
ALUE
ESET
0
0
0
0
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