MT47H32M16HR-25E AIT:G Micron, MT47H32M16HR-25E AIT:G Datasheet - Page 97

• Manufacturer Part Number: MT47H32M16HR-25E AIT:G
• Description: DRAM Chip DDR2 SDRAM 512M-Bit 32Mx16 1.8V 84-Pin FBGA
• Manufacturer: Micron

Figure 52: x4, x8 Data Output Timing –
PDF: 09005aef8440dbbc
512mbddr2_ait_aat.pdf – Rev. C 7/11 EN
DQ (first data no longer valid)
DQ (first data no longer valid)
All DQs and DQS collectively 6
DQ (last data valid)
DQ (last data valid)
Notes:
Earliest signal transition
Latest signal transition
DQS#
DQS 3
1.
2.
3. DQ transitioning after the DQS transition defines the
4. DQ0, DQ1, DQ2, DQ3 for x4 or DQ[7:0] for x8.
5.
6. The data valid window is derived for each DQS transition and is defined as
CK#
DQ 4
DQ 4
DQ 4
DQ 4
DQ 4
DQ 4
CK
t
t
transitions, and ends with the last valid transition of DQ.
T2 and at T2n are “early DQS,” at T3 are “nominal DQS,” and at T3n are “late DQS.”
t
HP is the lesser of
DQSQ is derived at each DQS clock edge, is not cumulative over time, begins with DQS
QH is derived from
T1
Micron Confidential and Proprietary
t HP 1
t
DQSQ,
t
CL or
t HP 1
t
HP:
t DQSQ 2
t
QH, and Data Valid Window
t QH 5
t
t
QH =
CH clock transitions collectively when a bank is active.
97
T2
512Mb: x8, x16 Automotive DDR2 SDRAM
window
Data
valid
T2
T2
T2
t HP 1
t
HP -
t DQSQ 2
T2n
t QHS
t
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t QH 5
QHS.
window
t HP 1
T2n
Data
valid
T2n
T2n
T3
t DQSQ 2
t QHS
t QH 5
t HP 1
t
window
DQSQ window. DQS transitions at
Data
valid
T3
T3
T3
T3n
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t DQSQ 2
t QHS
t QH 5
t HP 1
window
T4
Data
valid
T3n
T3n
T3n
t
QH -
t QHS
READ
t
DQSQ.