MT47H32M16HR-25E AIT:G Micron, MT47H32M16HR-25E AIT:G Datasheet - Page 101

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MT47H32M16HR-25E AIT:G

Manufacturer Part Number
MT47H32M16HR-25E AIT:G
Description
DRAM Chip DDR2 SDRAM 512M-Bit 32Mx16 1.8V 84-Pin FBGA
Manufacturer
Micron
Datasheet
Figure 55: Write Burst
PDF: 09005aef8440dbbc
512mbddr2_ait_aat.pdf – Rev. C 7/11 EN
Notes:
DQS, DQS#
DQS, DQS#
DQS, DQS#
Command
t
t
t
DQSS (NOM)
DQSS (MIN)
DQSS (MAX)
1. Subsequent rising DQS signals must align to the clock within
2. DI b = data-in for column b.
3. Three subsequent elements of data-in are applied in the programmed order following
4. Shown with BL = 4, AL = 0, CL = 3; thus, WL = 2.
5. A10 is LOW with the WRITE command (auto precharge is disabled).
Address
DI b.
CK#
DM
DM
DM
DQ
DQ
DQ
CK
Micron Confidential and Proprietary
Bank a,
WRITE
Col b
T0
WL ± t DQSS
WL - t DQSS
WL + t DQSS
NOP
T1
101
512Mb: x8, x16 Automotive DDR2 SDRAM
DI
b
NOP
T2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
DI
b
DI
b
Transitioning Data
T2n
t DQSS 5
T3
NOP
5
t DQSS 5
T3n
‹ 2010 Micron Technology, Inc. All rights reserved.
t
NOP
DQSS.
T4
Don’t Care
WRITE

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