MT47H32M16HR-25E AIT:G Micron, MT47H32M16HR-25E AIT:G Datasheet - Page 77

• Manufacturer Part Number: MT47H32M16HR-25E AIT:G
• Description: DRAM Chip DDR2 SDRAM 512M-Bit 32Mx16 1.8V 84-Pin FBGA
• Manufacturer: Micron

Extended Mode Register (EMR)
Figure 35: EMR Definition
PDF: 09005aef8440dbbc
512mbddr2_ait_aat.pdf – Rev. C 7/11 EN
Notes:
The extended mode register controls functions beyond those controlled by the mode
register; these additional functions are DLL enable/disable, output drive strength, on-
die termination (ODT), posted AL, off-chip driver impedance calibration (OCD), DQS#
enable/disable, RDQS/RDQS# enable/disable, and output disable/enable. These func-
tions are controlled via the bits shown in Figure 35. The EMR is programmed via the LM
command and will retain the stored information until it is programmed again or the de-
vice loses power. Reprogramming the EMR will not alter the contents of the memory ar-
ray, provided it is performed correctly.
The EMR must be loaded when all banks are idle and no bursts are in progress, and the
controller must wait the specified time
tion. Violating either of these requirements could result in an unspecified operation.
BA2
E15
0
16
0
0
1
1
1. E16 (BA2) is only applicable for densities 1Gb, reserved for future use, and must be pro-
2. Mode bits (En) with corresponding address balls (An) greater than E12 (A12) are re-
3. Not all listed AL options are supported in any individual speed grade.
4. As detailed in the Initialization (page 83) section notes, during initialization of the
1
BA1
E14
15
MRS
0
1
0
1
E12
grammed to “0.”
served for future use and must be programmed to “0.”
OCD operation, all three bits must be set to “1” for the OCD default state, then set to
“0” before initialization is finished.
0
1
14
BA0
E9
Extended mode register (EMR2)
Extended mode register (EMR3)
0
0
0
1
1
E11
Extended mode register (EMR)
0
1
Disabled
Outputs
Enabled
0
E8
n
An
0
0
1
0
1
RDQS Enable
E10
Mode register (MR)
0
1
Out
Mode Register Set
2
E7
12
0
1
0
0
1
Yes
A12
No
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DQS# Enable
RDQS
Disable
Enable
OCD Operation
OCD exit
Reserved
Reserved
Reserved
Enable OCD defaults
11
DQS#
10
A10
OCD Program
9
A9
E6
0
0
1
1
4
8
A8
E2
0
1
0
1
7
A7 A6 A5 A4 A3
R
R
TT
R
TT
TT
6
(Nominal)
disabled
150Ÿ
75Ÿ
50Ÿ
Posted CAS# R
5
77
512Mb: x8, x16 Automotive DDR2 SDRAM
E5
0
0
0
0
1
1
1
1
4
E4
0
0
1
1
0
0
1
1
3
E3
0
1
0
1
0
1
0
1
TT
2
A2 A1 A0
Posted CAS# Additive Latency (AL)
ODS
E1
0
1
t
Micron Technology, Inc. reserves the right to change products or specifications without notice.
1
MRD before initiating any subsequent opera-
DLL
E0
0
1
Output Drive Strength
0
Disable (test/debug)
Reserved
Enable (normal)
Extended Mode Register (EMR)
Address bus
Extended mode
register (Ex)
Reduced
DLL Enable
0
1
2
3
4
5
6
Full
3
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