MT47H32M16HR-25E AIT:G Micron, MT47H32M16HR-25E AIT:G Datasheet - Page 6

• Manufacturer Part Number: MT47H32M16HR-25E AIT:G
• Description: DRAM Chip DDR2 SDRAM 512M-Bit 32Mx16 1.8V 84-Pin FBGA
• Manufacturer: Micron

List of Figures
Figure 1: 512Mb DDR2 Part Numbers ............................................................................................................... 2
Figure 2: Simplified State Diagram ................................................................................................................... 8
Figure 3: 64 Meg x 8 Functional Block Diagram ............................................................................................... 11
Figure 4: 32 Meg x 16 Functional Block Diagram ............................................................................................. 12
Figure 5: 60-Ball FBGA – x4, x8 Ball Assignments (Top View) ........................................................................... 13
Figure 6: 84-Ball FBGA – x16 Ball Assignments (Top View) ............................................................................... 14
Figure 7: 84-Ball FBGA (8mm x 12.5mm) – x16 ................................................................................................ 17
Figure 8: 60-Ball FBGA (8mm x 10mm) – x4, x8 ............................................................................................... 18
Figure 9: Example Temperature Test Point Location ........................................................................................ 21
Figure 10: Single-Ended Input Signal Levels ................................................................................................... 41
Figure 11: Differential Input Signal Levels ...................................................................................................... 42
Figure 12: Differential Output Signal Levels .................................................................................................... 44
Figure 13: Output Slew Rate Load .................................................................................................................. 45
Figure 14: Full Strength Pull-Down Characteristics ......................................................................................... 46
Figure 15: Full Strength Pull-Up Characteristics .............................................................................................. 47
Figure 16: Reduced Strength Pull-Down Characteristics .................................................................................. 48
Figure 17: Reduced Strength Pull-Up Characteristics ...................................................................................... 49
Figure 18: Input Clamp Characteristics .......................................................................................................... 50
Figure 19: Overshoot ..................................................................................................................................... 51
Figure 20: Undershoot ................................................................................................................................... 51
Figure 21: Nominal Slew Rate for
Figure 22: Tangent Line for
Figure 23: Nominal Slew Rate for
Figure 24: Tangent Line for
Figure 25: Nominal Slew Rate for
Figure 26: Tangent Line for
Figure 27: Nominal Slew Rate for
Figure 28: Tangent Line for
Figure 29: AC Input Test Signal Waveform Command/Address Balls ................................................................ 64
Figure 30: AC Input Test Signal Waveform for Data with DQS, DQS# (Differential) ............................................ 64
Figure 31: AC Input Test Signal Waveform for Data with DQS (Single-Ended) ................................................... 65
Figure 32: AC Input Test Signal Waveform (Differential) .................................................................................. 65
Figure 33: MR Definition ............................................................................................................................... 73
Figure 34: CL ................................................................................................................................................. 76
Figure 35: EMR Definition ............................................................................................................................. 77
Figure 36: READ Latency ............................................................................................................................... 80
Figure 37: WRITE Latency .............................................................................................................................. 80
Figure 38: EMR2 Definition ........................................................................................................................... 81
Figure 39: EMR3 Definition ........................................................................................................................... 82
Figure 40: DDR2 Power-Up and Initialization ................................................................................................. 83
Figure 41: Example: Meeting
Figure 42: Multibank Activate Restriction ....................................................................................................... 87
Figure 43: READ Latency ............................................................................................................................... 89
Figure 44: Consecutive READ Bursts .............................................................................................................. 90
Figure 45: Nonconsecutive READ Bursts ........................................................................................................ 91
Figure 46: READ Interrupted by READ ............................................................................................................ 92
Figure 47: READ-to-WRITE ............................................................................................................................ 92
Figure 48: READ-to-PRECHARGE – BL = 4 ...................................................................................................... 93
Figure 49: READ-to-PRECHARGE – BL = 8 ...................................................................................................... 93
Figure 50: Bank Read – Without Auto Precharge .............................................................................................. 95
PDF: 09005aef8440dbbc
512mbddr2_ait_aat.pdf – Rev. C 7/11 EN
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512Mb: x8, x16 Automotive DDR2 SDRAM
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