MT47H32M16HR-25E AIT:G Micron, MT47H32M16HR-25E AIT:G Datasheet - Page 5

• Manufacturer Part Number: MT47H32M16HR-25E AIT:G
• Description: DRAM Chip DDR2 SDRAM 512M-Bit 32Mx16 1.8V 84-Pin FBGA
• Manufacturer: Micron

List of Tables
Table 1: Key Timing Parameters ....................................................................................................................... 1
Table 2: Addressing ......................................................................................................................................... 2
Table 3: FBGA 84-Ball – x16 and 60-Ball – x4, x8 Descriptions .......................................................................... 15
Table 4: Input Capacitance ............................................................................................................................ 19
Table 5: Absolute Maximum DC Ratings ......................................................................................................... 20
Table 6: Temperature Limits .......................................................................................................................... 21
Table 7: Thermal Impedance ......................................................................................................................... 22
Table 8: General I
Table 9: I
Table 10: DDR2 I
Table 11: AC Operating Specifications and Conditions .................................................................................... 27
Table 12: Recommended DC Operating Conditions (SSTL_18) ........................................................................ 39
Table 13: ODT DC Electrical Characteristics ................................................................................................... 40
Table 14: Input DC Logic Levels ..................................................................................................................... 41
Table 15: Input AC Logic Levels ...................................................................................................................... 41
Table 16: Differential Input Logic Levels ......................................................................................................... 42
Table 17: Differential AC Output Parameters ................................................................................................... 44
Table 18: Output DC Current Drive ................................................................................................................ 44
Table 19: Output Characteristics .................................................................................................................... 45
Table 20: Full Strength Pull-Down Current (mA) ............................................................................................. 46
Table 21: Full Strength Pull-Up Current (mA) .................................................................................................. 47
Table 22: Reduced Strength Pull-Down Current (mA) ...................................................................................... 48
Table 23: Reduced Strength Pull-Up Current (mA) .......................................................................................... 49
Table 24: Input Clamp Characteristics ............................................................................................................ 50
Table 25: Address and Control Balls ................................................................................................................ 51
Table 26: Clock, Data, Strobe, and Mask Balls ................................................................................................. 51
Table 27: AC Input Test Conditions ................................................................................................................ 52
Table 28: DDR2-400/533 Setup and Hold Time Derating Values (
Table 29: DDR2-667/800/1066 Setup and Hold Time Derating Values (
Table 30: DDR2-400/533
Table 31: DDR2-667/800/1066
Table 32: Single-Ended DQS Slew Rate Derating Values Using
Table 33: Single-Ended DQS Slew Rate Fully Derated (DQS, DQ at V
Table 34: Single-Ended DQS Slew Rate Fully Derated (DQS, DQ at V
Table 35: Single-Ended DQS Slew Rate Fully Derated (DQS, DQ at V
Table 36: Truth Table – DDR2 Commands ...................................................................................................... 66
Table 37: Truth Table – Current State Bank n – Command to Bank n ................................................................ 67
Table 38: Truth Table – Current State Bank n – Command to Bank m ............................................................... 69
Table 39: Minimum Delay with Auto Precharge Enabled ................................................................................. 70
Table 40: Burst Definition .............................................................................................................................. 74
Table 41: READ Using Concurrent Auto Precharge .......................................................................................... 94
Table 42: WRITE Using Concurrent Auto Precharge ....................................................................................... 100
Table 43: Truth Table – CKE .......................................................................................................................... 115
PDF: 09005aef8440dbbc
512mbddr2_ait_aat.pdf – Rev. C 7/11 EN
DD7
Timing Patterns (8-Bank Interleave READ Operation) ................................................................. 24
DD
DD
Specifications and Conditions ......................................................................................... 25
Parameters ..................................................................................................................... 23
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DH Derating Values with Differential Strobe ...................................................... 58
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DH Derating Values with Differential Strobe ............................................. 59
Micron Confidential and Proprietary
5
512Mb: x8, x16 Automotive DDR2 SDRAM
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
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) at DDR2-667 ...................................... 60
) at DDR2-533 ...................................... 61
) at DDR2-400 ...................................... 61
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................................................... 60
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