MT47H32M16HR-25E AIT:G Micron, MT47H32M16HR-25E AIT:G Datasheet - Page 8

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MT47H32M16HR-25E AIT:G

Manufacturer Part Number
MT47H32M16HR-25E AIT:G
Description
DRAM Chip DDR2 SDRAM 512M-Bit 32Mx16 1.8V 84-Pin FBGA
Manufacturer
Micron
Datasheet
State Diagram
Figure 2: Simplified State Diagram
PDF: 09005aef8440dbbc
512mbddr2_ait_aat.pdf – Rev. C 7/11 EN
Setting
default
EMRS
MRS
OCD
Note:
WRITE
precharge
WRITE A
Writing
Writing
(E)MRS
with
auto
1. This diagram provides the basic command flow. It is not comprehensive and does not
identify all timing requirements or possible command restrictions such as multibank in-
teraction, power down, entry/exit, etc.
power-
Active
down
Automatic Sequence
Command Sequence
Micron Confidential and Proprietary
WRITE
PRE
Initialization
precharged
Precharging
sequence
PRE, PRE_A
Activating
all banks
active
Bank
Idle
ACT
8
512Mb: x8, x16 Automotive DDR2 SDRAM
READ
ACT = ACTIVATE
CKE_H = CKE HIGH, exit power-down or self refresh
CKE_L = CKE LOW, enter power-down
(E)MRS = (Extended) mode register set
PRE = PRECHARGE
PRE_A = PRECHARGE ALL
READ = READ
READ A = READ with auto precharge
REFRESH = REFRESH
SR = SELF REFRESH
WRITE = WRITE
WRITE A = WRITE with auto precharge
Micron Technology, Inc. reserves the right to change products or specifications without notice.
Precharge
power-
down
precharge
Reading
READ A
Reading
with
auto
REFRESH
refreshing
CKE_L
Self
READ
CKE_L
Refreshing
‹ 2010 Micron Technology, Inc. All rights reserved.
State Diagram

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