MT47H32M16HR-25E AIT:G Micron, MT47H32M16HR-25E AIT:G Datasheet - Page 7

• Manufacturer Part Number: MT47H32M16HR-25E AIT:G
• Description: DRAM Chip DDR2 SDRAM 512M-Bit 32Mx16 1.8V 84-Pin FBGA
• Manufacturer: Micron

Micron Confidential and Proprietary
512Mb: x8, x16 Automotive DDR2 SDRAM
Features
Figure 51: Bank Read – with Auto Precharge ................................................................................................... 96
t
t
Figure 52: x4, x8 Data Output Timing –
DQSQ,
QH, and Data Valid Window ................................................... 97
t
t
Figure 53: x16 Data Output Timing –
DQSQ,
QH, and Data Valid Window ...................................................... 98
t
t
Figure 54: Data Output Timing –
AC and
DQSCK .......................................................................................... 99
Figure 55: Write Burst ................................................................................................................................... 101
Figure 56: Consecutive WRITE-to-WRITE ...................................................................................................... 102
Figure 57: Nonconsecutive WRITE-to-WRITE ................................................................................................ 102
Figure 58: WRITE Interrupted by WRITE ....................................................................................................... 103
Figure 59: WRITE-to-READ ........................................................................................................................... 104
Figure 60: WRITE-to-PRECHARGE ................................................................................................................ 105
Figure 61: Bank Write – Without Auto Precharge ............................................................................................ 106
Figure 62: Bank Write – with Auto Precharge .................................................................................................. 107
Figure 63: WRITE – DM Operation ................................................................................................................ 108
Figure 64: Data Input Timing ........................................................................................................................ 109
Figure 65: Refresh Mode ............................................................................................................................... 110
Figure 66: Self Refresh .................................................................................................................................. 112
Figure 67: Power-Down ................................................................................................................................ 114
Figure 68: READ-to-Power-Down or Self Refresh Entry .................................................................................. 116
Figure 69: READ with Auto Precharge-to-Power-Down or Self Refresh Entry ................................................... 116
Figure 70: WRITE-to-Power-Down or Self Refresh Entry ................................................................................. 117
Figure 71: WRITE with Auto Precharge-to-Power-Down or Self Refresh Entry .................................................. 117
Figure 72: REFRESH Command-to-Power-Down Entry .................................................................................. 118
Figure 73: ACTIVATE Command-to-Power-Down Entry ................................................................................. 118
Figure 74: PRECHARGE Command-to-Power-Down Entry ............................................................................. 119
Figure 75: LOAD MODE Command-to-Power-Down Entry ............................................................................. 119
Figure 76: Input Clock Frequency Change During Precharge Power-Down Mode ............................................ 120
Figure 77: RESET Function ........................................................................................................................... 122
Figure 78: ODT Timing for Entering and Exiting Power-Down Mode ............................................................... 124
Figure 79: Timing for MRS Command to ODT Update Delay .......................................................................... 125
Figure 80: ODT Timing for Active or Fast-Exit Power-Down Mode .................................................................. 125
Figure 81: ODT Timing for Slow-Exit or Precharge Power-Down Modes .......................................................... 126
Figure 82: ODT Turn-Off Timings When Entering Power-Down Mode ............................................................ 126
Figure 83: ODT Turn-On Timing When Entering Power-Down Mode .............................................................. 127
Figure 84: ODT Turn-Off Timing When Exiting Power-Down Mode ................................................................ 128
Figure 85: ODT Turn-On Timing When Exiting Power-Down Mode ................................................................. 129
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512mbddr2_ait_aat.pdf – Rev. C 7/11 EN