MT47H32M16HR-25E AIT:G Micron, MT47H32M16HR-25E AIT:G Datasheet - Page 79

• Manufacturer Part Number: MT47H32M16HR-25E AIT:G
• Description: DRAM Chip DDR2 SDRAM 512M-Bit 32Mx16 1.8V 84-Pin FBGA
• Manufacturer: Micron

On-Die Termination (ODT)
Off-Chip Driver (OCD) Impedance Calibration
Posted CAS Additive Latency (AL)
PDF: 09005aef8440dbbc
512mbddr2_ait_aat.pdf – Rev. C 7/11 EN
ODT effective resistance, R
Figure 35 (page 77). The ODT feature is designed to improve signal integrity of the
memory channel by allowing the DDR2 SDRAM controller to independently turn on/off
ODT for any or all devices. R
lectable and apply to each DQ, DQS/DQS#, RDQS/RDQS#, UDQS/UDQS#, LDQS/
LDQS#, DM, and UDM/LDM signals. Bits (E6, E2) determine what ODT resistance is en-
abled by turning on/off “sw1,” “sw2,” or “sw3.” The ODT effective resistance value is se-
lected by enabling switch “sw1,” which enables all R1 values that are 150 each, ena-
bling an effective resistance of 75 (R
R2 values that are 300 each, enable an effective ODT resistance of 150
(R
of 50 . Reserved states should not be used, as an unknown operation or incompatibility
with future versions may result.
The ODT control ball is used to determine when R
ODT has been enabled via bits E2 and E6 of the EMR. The ODT feature and ODT input
ball are only used during active, active power-down (both fast-exit and slow-exit
modes), and precharge power-down modes of operation.
ODT must be turned off prior to entering self refresh mode. During power-up and initi-
alization of the DDR2 SDRAM, ODT should be disabled until the EMR command is is-
sued. This will enable the ODT feature, at which point the ODT ball will determine the
R
HIGH until eight clocks after the EMR has been enabled (see Figure 78 (page 124) for
ODT timing diagrams).
The OFF-CHIP DRIVER function is an optional DDR2 JEDEC feature not supported by
Micron and thereby must be set to the default state. Enabling OCD beyond the default
settings will alter the I/O drive characteristics and the timing and output I/O specifica-
tions will no longer be valid (see Initialization (page 83) for proper setting of OCD de-
faults).
Posted CAS additive latency (AL) is supported to make the command and data bus effi-
cient for sustainable bandwidths in DDR2 SDRAM. Bits E3–E5 define the value of AL, as
shown in Figure 35. Bits E3–E5 allow the user to program the DDR2 SDRAM with an AL
of 0, 1, 2, 3, 4, 5, or 6 clocks. Reserved states should not be used as an unknown opera-
tion or incompatibility with future versions may result.
In this operation, the DDR2 SDRAM allows a READ or WRITE command to be issued
prior to
using this feature would set AL =
is held for the time of the AL before it is issued internally to the DDR2 SDRAM device.
RL is controlled by the sum of AL and CL; RL = AL + CL. WRITE latency (WL) is equal to
RL minus one clock; WL = AL + CL - 1 ×
(page 80). An example of a WL is shown in Figure 37 (page 80).
TT(EFF)
TT2[EFF]
t
value. Anytime the EMR enables the ODT function, ODT may not be driven
RCD (MIN) with the requirement that AL
= R2/2). Switch “sw3” enables R1 values of 100 , enabling effective resistance
Micron Confidential and Proprietary
TT(EFF)
TT
79
512Mb: x8, x16 Automotive DDR2 SDRAM
effective resistance values of 50   , and 150 are se-
t
, is defined by bits E2 and E6 of the EMR, as shown in
RCD (MIN) - 1 ×
TT2 [EFF]
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
CK. An example of RL is shown in Figure 36
Extended Mode Register (EMR)
= R2/2). Similarly, if “sw2” is enabled, all
TT(EFF)
t
CK. The READ or WRITE command
t
RCD (MIN). A typical application
is turned on and off, assuming
‹ 2010 Micron Technology, Inc. All rights reserved.