HD6437101 RENESAS [Renesas Technology Corp], HD6437101 Datasheet - Page 70

• Manufacturer Part Number: HD6437101
• Description: 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 2 CPU
Note:
Rev.1.00 Sep. 18, 2008 Page 36 of 522
REJ09B0069-0100
Instruction
DMULU.L Rm,Rn
DT
EXTS.B
EXTS.W
EXTU.B
EXTU.W
MAC.L
MAC.W
MUL.L
MULS.W
MULU.W
NEG
NEGC
SUB
SUBC
SUBV
* The normal number of execution states is shown. (The number in parentheses is the
Rn
Rm,Rn
Rm,Rn
Rm,Rn
Rm,Rn
@Rm+,@Rn+ 0000nnnnmmmm1111
@Rm+,@Rn+ 0100nnnnmmmm1111
Rm,Rn
Rm,Rn
Rm,Rn
Rm,Rn
Rm,Rn
Rm,Rn
Rm,Rn
Rm,Rn
number of states when there is contention with the preceding or following instructions.)
Instruction Code
0011nnnnmmmm0101
0100nnnn00010000
0110nnnnmmmm1110
0110nnnnmmmm1111
0110nnnnmmmm1100
0110nnnnmmmm1101
0000nnnnmmmm0111
0010nnnnmmmm1111
0010nnnnmmmm1110
0110nnnnmmmm1011
0110nnnnmmmm1010
0011nnnnmmmm1000
0011nnnnmmmm1010
0011nnnnmmmm1011
Operation
Unsigned operation of
Rn × Rm → MACH,
MACL 32 × 32 → 64 bits
Rn – 1 → Rn, when Rn
is 0, 1 → T. When Rn is
nonzero, 0 → T
Byte in Rm is sign-
extended → Rn
Word in Rm is sign-
extended → Rn
Byte in Rm is zero-
extended → Rn
Word in Rm is zero-
extended → Rn
Signed operation of
(Rn) × (Rm) + MAC →
MAC 32 × 32 + 64 →
64 bits
Signed operation of
(Rn) × (Rm) + MAC →
MAC 16 × 16 + 64 →
64 bits
Rn × Rm → MACL,
32 × 32 → 32 bits
Signed operation of
Rn × Rm → MACL 16 ×
16 → 32 bits
Unsigned operation of
Rn × Rm → MACL 16 ×
16 → 32 bits
0 – Rm → Rn
0 – Rm – T → Rn,
Borrow → T
Rn – Rm → Rn
Rn – Rm – T → Rn,
Borrow → T
Rn – Rm → Rn,
Underflow → T
Execu-
tion
States
2 to 4*
1
1
1
1
1
3/
(2 to 4)*
3/(2)*
2 to 4*
1 to 3*
1 to 3*
1
1
1
1
1
—
Borrow
Overflow
T Bit
—
Comparison
result
—
—
—
—
—
—
—
—
—
—
Borrow