HD6437101 RENESAS [Renesas Technology Corp], HD6437101 Datasheet - Page 101

• Manufacturer Part Number: HD6437101
• Description: 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

5.4.2
The interrupt priority is predetermined. When multiple interrupts occur simultaneously
(overlapped interruptions), the interrupt controller (INTC) determines their relative priorities and
starts the exception processing according to the results.
The priority of interrupts is expressed as priority levels 0 to 16, with priority 0 the lowest and
priority 16 the highest. The NMI interrupt has priority 16 and cannot be masked, so it is always
accepted. IRQ interrupt and on-chip peripheral module interrupt priority levels can be set freely
using the INTC’s interrupt priority registers A, D to K (IPRA, IPRD to IPRK) as shown in table
5.8. The priority levels that can be set are 0 to 15. Level 16 cannot be set. See section 6.3.4,
Interrupt Priority Registers A, D to K (IPRA, IPRD to IPRK), for more information on IPRA,
IPRD to IPRK.
Table 5.8
5.4.3
When an interrupt occurs, the interrupt controller (INTC) ascertains its priority level. NMI is
always accepted, but other interrupts are only accepted if they have a priority level higher than the
priority level set in the interrupt mask bits (I3 to I0) in the status register (SR).
When an interrupt is accepted, exception processing begins. In interrupt exception processing, the
CPU saves SR and the program counter (PC) to the stack. The priority level value of the accepted
interrupt is written to SR bits I3 to I0. For NMI, however, the priority level is 16, but the value set
in I3 to I0 is H'F (level 15). Next, the start address of the exception service routine is fetched from
the exception processing vector table for the accepted interrupt, that address is jumped to and
execution begins. See section 6.6, Interrupt Operation, for more information on the interrupt
exception processing.
5.5
5.5.1
Exception processing can be triggered by trap instruction, illegal slot instructions, and general
illegal instructions, as shown in table 5.9.
Type
NMI
IRQ
On-chip peripheral module
Interrupt Priority Level
Interrupt Exception Processing
Exceptions Triggered by Instructions
Types of Exceptions Triggered by Instructions
Interrupt Priority
Priority Level
16
0 to 15
Comment
Fixed priority level. Cannot be masked.
Set with interrupt priority registers A, D to K
(IPRA, IPRD to IPRK).
Rev.1.00 Sep. 18, 2008 Page 67 of 522
Section 5 Exception Processing
REJ09B0069-0100