HD6437101 RENESAS [Renesas Technology Corp], HD6437101 Datasheet - Page 57

• Manufacturer Part Number: HD6437101
• Description: 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Table 2.8
Addressing
Mode
Direct register
addressing
Indirect register
addressing
Post-increment
indirect register
addressing
Pre-decrement
indirect register
addressing
Indirect register
addressing with
displacement
Addressing Modes and Effective Addresses
Instruction
Format
Rn
@Rn
@Rn+
@-Rn
@(disp:4,
Rn)
Effective Address Calculation
The effective address is register Rn. (The operand
is the contents of register Rn.)
The effective address is the contents of register
Rn.
The effective address is the contents of register
Rn.
A constant is added to the content of Rn after the
instruction is executed. 1 is added for a byte
operation, 2 for a word operation, and 4 for a
longword operation.
The effective address is the value obtained by
subtracting a constant from Rn. 1 is subtracted for
a byte operation, 2 for a word operation, and 4 for
a longword operation.
The effective address is the sum of Rn and a 4-bit
displacement (disp). The value of disp is zero-
extended, and remains unchanged for a byte
operation, is doubled for a word operation, and is
quadrupled for a longword operation.
(zero-extended)
1/2/4
1/2/4
Rn
Rn
Rn
1/2/4
disp
Rn
Rn + 1/2/4
Rn – 1/2/4
×
+
–
+
Rev.1.00 Sep. 18, 2008 Page 23 of 522
Rn + disp × 1/2/4
Rn – 1/2/4
Rn
Rn
REJ09B0069-0100
Equation
—
Rn
Rn
(After the
instruction
executes)
Byte:
Rn + 1 → Rn
Word:
Rn + 2 → Rn
Longword:
Rn + 4 → Rn
Byte:
Rn – 1 → Rn
Word:
Rn – 2 → Rn
Longword:
Rn – 4 → Rn
(Instruction is
executed with
Rn after this
calculation)
Byte:
Rn + disp
Word:
Rn + disp × 2
Longword:
Rn + disp × 4
Section 2 CPU