HD6437101 RENESAS [Renesas Technology Corp], HD6437101 Datasheet - Page 102

• Manufacturer Part Number: HD6437101
• Description: 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 5 Exception Processing
Table 5.9
5.5.2
When a TRAPA instruction is executed, trap instruction exception processing starts. The CPU
operates as follows:
1. The status register (SR) is saved to the stack.
2. The program counter (PC) is saved to the stack. The PC value saved is the start address of the
3. The CPU reads the start address of the exception service routine from the exception processing
5.5.3
An instruction placed immediately after a delayed branch instruction is called ″instruction placed
in a delay slot″. When the instruction placed in the delay slot is an undefined code, illegal slot
exception processing starts after the undefined code is decoded. Illegal slot exception processing
also starts when an instruction that rewrites the program counter (PC) is placed in a delay slot and
the instruction is decoded. The CPU handles an illegal slot instruction as follows:
1. The status register (SR) is saved to the stack.
2. The program counter (PC) is saved to the stack. The PC value saved is the target address of the
3. The start address of the exception service routine is fetched from the exception processing
Rev.1.00 Sep. 18, 2008 Page 68 of 522
REJ09B0069-0100
Type
Trap instruction
Illegal slot
instructions
General illegal
instructions
instruction to be executed after the TRAPA instruction.
vector table that corresponds to the vector number specified in the TRAPA instruction, jumps
to that address and starts executing the program. This jump is not a delayed branch.
delayed branch instruction immediately before the undefined code or the instruction that
rewrites the PC.
vector table that corresponds to the exception that occurred. That address is jumped to and the
program starts executing. The jump in this case is not a delayed branch.
Trap Instructions
Illegal Slot Instructions
Types of Exceptions Triggered by Instructions
Source Instruction
TRAPA
Undefined code placed
immediately after a delayed
branch instruction (delay slot) or
instructions that rewrite the PC
Undefined code anywhere
besides in a delay slot
Comment
⎯
Delayed branch instructions: JMP, JSR,
BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF,
BRAF
Instructions that rewrite the PC: JMP, JSR,
BRA, BSR, RTS, RTE, BT, BF, TRAPA,
BF/S, BT/S, BSRF, BRAF
⎯