HD6437101 RENESAS [Renesas Technology Corp], HD6437101 Datasheet - Page 309

• Manufacturer Part Number: HD6437101
• Description: 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

9.3.3
RSTCSR is an 8-bit readable/writable register that controls the generation of the internal reset
signal when TCNT overflows, and selects the type of internal reset signal.
Note:
Bit
7
6
5
4 to 0
* Only 0 can be written, for flag clearing.
Bit Name
WOVF
RSTE
RSTS
—
Reset Control/Status Register (RSTCSR)
Initial
Value
0
0
0
All 1
R/W
R/(W)*
R/W
R/W
R
Description
Watchdog Overflow Flag
This bit is set when TCNT overflows in watchdog timer
mode. This bit cannot be set in interval timer mode.
[Setting condition]
•
[Clearing condition]
•
Reset Enable
Specifies whether or not a reset signal is generated in
the chip if TCNT overflows in watchdog timer mode.
0: Reset signal is not generated even if TCNT overflows
1: Reset signal is generated if TCNT overflows
Reset Select
Selects the type of internal reset generated if TCNT
overflows in watchdog timer mode.
0: Power-on reset
1: Manual reset
Reserved
These bits are always read as 1. The write value should
always be 1.
(Though this LSI is not reset, TCNT and TCSR in
WDT are reset)
Set when TCNT overflows in watchdog timer mode
Cleared by reading WOVF, and then writing 0 to
WOVF
Rev.1.00 Sep. 18, 2008 Page 275 of 522
Section 9 Watchdog Timer
REJ09B0069-0100