HD6437101 RENESAS [Renesas Technology Corp], HD6437101 Datasheet - Page 156

• Manufacturer Part Number: HD6437101
• Description: 32-Bit RISC Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 8 Multifunction Timer Pulse Unit (MTU)
• Timer gate control register (TGCR)
• Timer cycle data register (TCDR)
• Timer dead time data register (TDDR)
• Timer subcounter (TCNTS)
• Timer cycle buffer register (TCBR)
8.3.1
The TCR registers are 8-bit readable/writable registers that control the TCNT operation for each
channel. The MTU has a total of five TCR registers, one for each channel (channel 0 to 4). TCR
register settings should be conducted only when TCNT operation is stopped.
Rev.1.00 Sep. 18, 2008 Page 122 of 522
REJ09B0069-0100
Bit
7
6
5
4
3
2
1
0
Bit Name
CCLR2
CCLR1
CCLR0
CKEG1
CKEG0
TPSC2
TPSC1
TPSC0
Timer Control Register (TCR)
Initial
value
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Counter Clear 2 to 0
These bits select the TCNT counter clearing source. See
tables 8.3 and 8.4 for details.
Clock Edge 1 and 0
These bits select the input clock edge. When the input clock
is counted using both edges, the input clock period is
halved (e.g. Pφ/4 both edges = φ/2 rising edge). If phase
counting mode is used on channels 1 and 2, this setting is
ignored and the phase counting mode setting has priority.
Internal clock edge selection is valid when the input clock is
Pφ/4 or slower. When Pφ/1, or the overflow/underflow of
another channel is selected for the input clock, although
values can be written, counter operation compiles with the
initial value.
00: Count at rising edge
01: Count at falling edge
1x: Count at both edges
Legend: x: Don’t care
Time Prescaler 2 to 0
These bits select the TCNT counter clock. The clock source
can be selected independently for each channel. See tables
8.5 to 8.8 for details.