HD6417706 RENESAS [Renesas Technology Corp], HD6417706 Datasheet - Page 79

• Manufacturer Part Number: HD6417706
• Description: Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

The instruction codes are listed from tables 2.5 to 2.10. Those tables are described according to the
following items.
Note: * Scaling ( 1, 2, 4) is performed according to the instruction operand size.
Item
Instruction
mnemonic
Instruction
code
Operation
summary
Privileged
mode
Execution
cycles
T bit
Format
OP.Sz SRC,DEST
MSB
(xx)
M/Q/T
&
|
^
~
<<n, >>n
,
LSB
Explanation
OP: Operation code
Sz: Size
SRC: Source
DEST: Destination
Rm: Source register
Rn: Destination register
imm: Immediate data
disp: Displacement
mmmm: Source register
nnnn: Destination register
iiii: Immediate data
dddd: Displacement*
Direction of transfer
Memory operand
Flag bits in SR
Logical AND of each bit
Logical OR of each bit
Exclusive OR of each bit
Logical NOT of each bit
n-bit shift
Indicates whether privileged mode applies
Value when no wait states are inserted
The execution cycles listed in the table are minimums. The
actual number of cycles may be increased in cases such as
the followings:
1. When contention occurs between instruction fetches and
2. When the destination register of the load instruction
Value of T bit after instruction is executed
—: No change
data access
(memory
instruction are the same
0000: R0
0001: R1
1111: R15
...........
register) and the register used by the next
Rev. 4.00, 03/04, page 33 of 660