HD6417706 RENESAS [Renesas Technology Corp], HD6417706 Datasheet - Page 626

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HD6417706

Manufacturer Part Number
HD6417706
Description
Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet

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24.3.2
Table 24.6 Control Signal Timing
Notes: 1. RESETP, NMI, and IRQ5 to IRQ0 are asynchronous. Changes are detected at the
Rev. 4.00, 03/04, page 580 of 660
Item
RESETP pulse width
RESETP setup time*
RESETP hold time
RESETM pulse width
RESETM setup time
RESETM hold time
BREQ setup time
BREQ hold time
NMI setup time *
NMI hold time
IRQ5 to IRQ0 setup time *
IRQ5 to IRQ0 hold time
IRQOUT delay time
BACK delay time
STATUS1, STATUS0 delay time
Bus tri-state delay time 1
Bus tri-state delay time 2
Bus buffer-on time 1
Bus buffer-on time 2
2. The upper limit of the external bus clock is 66 MHz.
3. In the standby mode, when XTAL oscillation continues, t
4. In the standby mode, t
Control Signal Timing
clock fall when the setup shown is used. When the setup cannot be used, detection
can be delayed until the next clock falls.
XTAL oscillation stops, t
µs).
When the clock multiplication ratio is changed, t
low until STATUS (0-1) changes to reset (HH). When the clock multiplication ratio is
changed, RESETM must be kept low until STATUS (0-1) changes to reset (HH).
1
1
1
RESMW
RESPW
= t
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
RESPW
RESPS
RESPH
RESMW
RESMS
RESMH
BREQS
BREQH
NMIS
NMIH
IRQS
IRQH
IRQOD
BACKD
STD
BOFF1
BOFF2
BON1
BON2
= t
OSC2
OSC2
(10 ms). In the sleep mode, RESETM must be kept
(10 ms). In the sleep mode, t
Min
20*
20
2
12*
6
34
6
4
10
4
10
4
0
0
0
0
3
4
RESPW
= t
RESPn
Max
10
10
10
15
15
15
15
PLL1
(100 µs).
= t
OSC1
RESPW
Unit
tcyc
ns
ns
tcyc
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(100µs), when
= t
PLL1
Figure
24.11,
24.12
24.14
24.12,
24.13
24.14,
24.15
(100

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