HD6417706 RENESAS [Renesas Technology Corp], HD6417706 Datasheet - Page 565

• Manufacturer Part Number: HD6417706
• Description: Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

21.3
The H-UDI has the following registers. Refer to section 23, List of Registers, for more details of
the addresses and access sizes.
21.3.1
The bypass register is a 1-bit register that cannot be accessed by the CPU. When the SDIR is set to
the bypass mode, the SDBPR is connected between H-UDI pins TDI and TDO.
21.3.2
The instruction register (SDIR) is a 16-bit read-only register. The register is in bypass mode in its
initial state. It is initialized by TRST or in the TAP test-logic-reset state, and can be written by the
H-UDI irrespective of the CPU mode. Operation is not guaranteed when a reserved command is
set to this register.
Note: X Don't care
Bit
15
14
13
12
11 to 0 —
Bypass register (SDBPR)
Instruction register (SDIR)
Boundary register (SDBSR)
Bit Name
TI3
TI2
TI1
TI0
Register Description
Bypass Register (SDBPR)
Instruction Register (SDIR)
Initial Value
1
1
1
1
All 1
R/W Description
R
R
R
R
R
Test Instruction Bits
Cannot be written by the CPU.
0000: EXTEST
0100: SAMPLE/PRELOAD
0101: Reserved (Setting prohibited)
0110: H-UDI reset negate
0111: H-UDI reset assert
100X: Reserved (Setting prohibited)
101X: H-UDI interrupt
110X: Reserved (Setting prohibited)
1110: Reserved (Setting prohibited)
1111: Bypass mode (initial value)
0001: Recovery from sleep
Reserved
These bits are always read as 1.
Rev. 4.00, 03/04, page 519 of 660