HD6417706 RENESAS [Renesas Technology Corp], HD6417706 Datasheet - Page 321

• Manufacturer Part Number: HD6417706
• Description: Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Operation
Cycle-Steal Mode
In the cycle-steal mode, the DREQ sampling timing is the same regardless of whether level or
edge detection is used.
For example, in figure 9.17 (cycle-steal mode, level detection), DMAC transfer begins, at the
earliest, three cycles after the first sampling is performed. The second sampling is started two
cycles after the first. If DREQ is not detected at this time, sampling is performed in each
subsequent cycle.
Thus, DREQ sampling is performed one step in advance. The third sampling operation is not
performed until the idle cycle following the end of the first DMA transfer.
The above conditions are the same whatever the number of CPU transfer cycles, as shown in
figure 9.18, and whatever the number of DMA transfer cycles, as shown in figure 9.19.
DACK is output in a read in the example in figure 9.17, and in a write in the example in figure
9.18. In both cases, DACK is output for the same duration as CSn.
Figure 9.20 illustrates the case where DREQ is not detected and sampling is subsequently
executed every cycle.
Figure 9.21 shows an example of edge detection in the cycle-steal mode.
Burst Mode, Level Detection
In the case of burst mode with level detection, the DREQ sampling timing is the same as in the
cycle-steal mode.
For example, in figure 9.22, DMAC transfer begins, at the earliest, three cycles after the first
sampling is performed. The second sampling is started two cycles after the first. Subsequent
sampling operations are performed in the idle cycle following the end of the DMA transfer
cycle.
In the burst mode, also, the DACK output period is the same as in the cycle-steal mode.
Burst Mode, Edge Detection
In the case of burst mode with edge detection, DREQ sampling is only performed once.
For example, in figure 9.23, DMAC transfer begins, at the earliest, three cycles after the first
sampling is performed. After this, DMAC transfer is executed continuously until the number of
data transfers set in the DMATCR register have been completed. DREQ is not sampled during
this time.
To restart DMA transfer after it has been suspended by an NMI, first clear NMIF, then input an
edge request again.
In the burst mode, also, the DACK output period is the same as in the cycle-steal mode.
Rev. 4.00, 03/04, page 275 of 660