HD6417706 RENESAS [Renesas Technology Corp], HD6417706 Datasheet - Page 226

• Manufacturer Part Number: HD6417706
• Description: Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Table 8.9
8.4.5
The individual memory control register (MCR) is a 16-bit read/write register that specifies RAS
and CAS timing and burst control for synchronous DRAM (areas 2 and 3), specifies address
multiplexing, and controls refresh. This enables direct connection of synchronous DRAM without
external circuits.
The MCR is initialized to H'0000 by power-on resets, but is not initialized by manual resets or
standby mode. The bits TPC1, TPC0, RCD1, RCD0, TRWL1, TRWL0, TRAS1, TRAS0, RASD
and AMX3 to AMX0 are written to at the initialization after a power-on reset and are not then
modified again. When RFSH and RMODE are written to, write the same values to the other bits.
When using synchronous DRAM, do not access areas 2 and 3 until this register is initialized.
Rev. 4.00, 03/04, page 180 of 660
WCR2's bits
Bit 2:
A0W2
0
1
Bit 1:
A0W1
0
1
0
1
Individual Memory Control Register (MCR)
Area 0 Wait Control
Bit 0:
A0W0
0
1
0
1
0
1
0
1
Inserted
Wait States
0
1
2
3
4
6
8
10
First Cycle
WAIT
WAIT Pin
Ignored
Enable
Enable
Enable
Enable
Enable
Enable
Enable
WAIT
WAIT
Description
Number of States
Per Data Transfer WAIT
2
2
3
4
4
6
8
10
(Excluding First Cycle)
Burst Cycle
WAIT
WAIT
WAIT Pin
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable