HD6417706 RENESAS [Renesas Technology Corp], HD6417706 Datasheet - Page 129

• Manufacturer Part Number: HD6417706
• Description: Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Notes: 1. Priorities are indicated from high to low, 1 being highest and 4 being lowest.
4.1.3
Processor resets and interrupts are asynchronous events unrelated to the instruction stream. All
exception events are prioritized to establish an acceptance order whenever two or more exception
events occur simultaneously. If a power-on reset and manual reset occur simultaneously, the
power-on reset takes precedence.
Exception
Type
General
exception
events
General
interrupt
requests
2. The user defines the break point traps. 1 is a break point before instruction execution
3. Use software to specify relative priorities of external hardware interrupts and peripheral
Acceptance of Exceptions
and 11 is a break point after instruction execution. For an operand break point, use 11.
module interrupts (see section 6, Interrupt Controller (INTC)).
Current
Instruction
Aborted
and retried
Completed
Completed
Exception Event
TLB protection violation
(instruction access)
General illegal instruction
exception
Illegal slot
instruction exception
CPU Address error
(data access)
TLB miss
(data access not in
repeat loop)
TLB invalid (data access) 2
TLB protection violation
(data access)
Initial page write
Unconditional trap
(TRAPA instruction)
User breakpoint trap
DMA address error
Nonmaskable interrupt
External hardware
interrupt
H-UDI interrupt
Priority*
2
2
2
2
2
2
2
2
2
2
3
4*
4*
3
3
1
Exception
Order
4
5
5
6
7
8
9
10
5
n*
12
—
—
—
2
Rev. 4.00, 03/04, page 83 of 660
Vector
Address
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Vector
Offset
H'00000100
H'00000100
H'00000100
H'00000100
H'00000400
H'00000100
H'00000100
H'00000100
H'00000100
H'00000100
H'00000100
H'00000600
H'00000600
H'00000600