HD6417706 RENESAS [Renesas Technology Corp], HD6417706 Datasheet - Page 23

• Manufacturer Part Number: HD6417706
• Description: Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 5 Cache................................................................................................. 99
5.1
5.2
5.3
5.4
Section 6 Interrupt Controller (INTC) .............................................................. 111
6.1
6.2
6.3
6.4
6.5
6.6
Section 7 User Break Controller ....................................................................... 135
7.1
7.2
Feature............................................................................................................................... 99
5.1.1
Register Description.......................................................................................................... 101
5.2.1
5.2.2
Operation........................................................................................................................... 104
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
5.3.6
Memory-Mapped Cache.................................................................................................... 107
5.4.1
5.4.2
5.4.3
Feature............................................................................................................................... 111
Input/Output Pin................................................................................................................ 113
Interrupt Sources ............................................................................................................... 113
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
Register Description.......................................................................................................... 121
6.4.1
6.4.2
6.4.3
6.4.4
6.4.5
6.4.6
Operation........................................................................................................................... 129
6.5.1
6.5.2
Interrupt Response Time ................................................................................................... 132
Feature............................................................................................................................... 135
Register Description.......................................................................................................... 137
7.2.1
Cache Structure.................................................................................................... 99
Cache Control Register (CCR) ............................................................................ 101
Cache Control Register 2 (CCR2)........................................................................ 102
Searching the Cache............................................................................................. 104
Read Access ......................................................................................................... 105
Prefetch Operation ............................................................................................... 106
Write Access ........................................................................................................ 106
Write-Back Buffer ............................................................................................... 106
Coherency of Cache and External Memory ......................................................... 107
Address Array ...................................................................................................... 107
Data Array............................................................................................................ 108
Usage Examples................................................................................................... 110
NMI Interrupts ..................................................................................................... 113
IRQ Interrupt........................................................................................................ 114
IRL Interrupts....................................................................................................... 115
On-Chip Peripheral Module Interrupts ................................................................ 116
Interrupt Exception Processing and Priority ........................................................ 117
Interrupt Priority Registers A to E (IPRA to IPRE)............................................. 121
Interrupt Control Register 0 (ICR0)..................................................................... 122
Interrupt Control Register 1 (ICR1)..................................................................... 123
Interrupt Request Register 0 (IRR0) .................................................................... 125
Interrupt Request Register 1 (IRR1) .................................................................... 127
Interrupt Request Register 2 (IRR2) .................................................................... 128
Interrupt Sequence ............................................................................................... 129
Multiple Interrupts ............................................................................................... 131
Break Address Register A (BARA) ..................................................................... 137
Rev. 4.00, 03/04, page xxiii of xlvi