HD6417706 RENESAS [Renesas Technology Corp], HD6417706 Datasheet - Page 147

• Manufacturer Part Number: HD6417706
• Description: Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

5.2
The cache includes the following registers. Refer to section 23, List of Registers, for more details
of the addresses and access sizes.
5.2.1
The cache is enabled or disabled using the CE bit of the cache control register (CCR). CCR also
has a CF bit (which invalidates all cache entries), and a WT and CB bits (which select either write-
through mode or write-back mode). Programs that change the contents of the CCR register should
be placed in address space that is not cached.
Bit
31 to 4
3
2
1
0
Cache control register (CCR)
Cache control register 2 (CCR2)
Register Description
Bit Name
CF
CB
WT
CE
Cache Control Register (CCR)
Initial Value
All 0
0
0
0
0
R/W
R
R
R/W
R/W
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Cache Flash
When 1 is set, the V, U and LRU bits of all cache
entries are cleared to 0 (flush).
This bit is always read as 0. Write-back to external
memory is not performed when the cache is flushed.
Cache Write-back
Indicates the cache's operating mode for area P1.
0: Write-through mode
1: Write-back mode
Write through
Indicates the cache's operating mode for area P0, U0,
and P3.
0: Write-back mode
1: Write-through mode
Cache enable
Indicates whether to use the cache function.
0: Cache not used
1: Cache used
Rev. 4.00, 03/04, page 101 of 660