HD6417706 RENESAS [Renesas Technology Corp], HD6417706 Datasheet - Page 68

• Manufacturer Part Number: HD6417706
• Description: Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

T bit: The T bit in the status register (SR) is used to indicate the result of compare operations, and
is read as a TRUE/FALSE condition determining if a conditional branch is taken or not. To
improve processing speed, the T bit logic state is modified only by specific operations. An
example of how the T bit may be used in a sequence of operations is shown below.
Literals: Byte-length literals are inserted directly into the instruction code as immediate data. To
maintain the 16-bit fixed-length instruction code, word or longword literals are stored in a table in
main memory rather than inserted directly into the instruction code. The memory table is accessed
by the MOV instruction using PC-relative addressing with displacement, as follows:
Absolute Addresses: As with word and longword literals, absolute addresses must also be stored
in a table in main memory. The value of the absolute address is transferred to a register and the
operand access is specified by indexed register-indirect addressing, with the absolute address
loaded (like word and longword immediate data) during instruction execution.
16-Bit and 32-Bit Displacements: In the same way, 16-bit and 32-bit displacements also must be
stored in a table in main memory. Exactly like absolute addresses, the displacement value is
transferred to a register and the operand access is specified by indexed register-indirect addressing,
loading the displacement (like word and longword immediate data) during instruction execution.
Rev. 4.00, 03/04, page 22 of 660
ADD
CMP/EQ
BT
MOV.W
#1, R0
R1, R0
TRGET
@(disp, PC), R0
;T bit not modified by ADD operation
;T bit set to 1 when R0
;branch taken to TRGET when T bit = 1 (R0 = 0)
0