HD6417706 RENESAS [Renesas Technology Corp], HD6417706 Datasheet - Page 44

• Manufacturer Part Number: HD6417706
• Description: Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 14 Serial Communication Interface (SCI)
Table 14.1
Table 14.2
Table 14.3
Table 14.4
Table 14.5
Table 14.6
Table 14.7
Table 14.8
Table 14.9
Table 14.10
Table 14.11
Table 14.12
Table 14.13
Section 15 Smart Card Interface
Table 15.1
Table 15.2
Table 15.3
Table 15.4
Table 15.5
Table 15.6
Table 15.7
Table 15.8
Section 16 Serial Communication Interface with FIFO (SCIF)
Table 16.1
Table 16.2
Table 16.3
Table 16.4
Table 16.5
Table 16.6
Table 16.7
Table 16.8
Table 16.9
Section 17 Pin Function Controller (PFC)
Table 17.1
Section 18 I/O Ports
Table 18.1
Table 18.2
Table 18.3
Rev. 4.00, 03/04, page xliv of xlvi
SCI Pins ................................................................................................................ 351
SCSMR Settings ................................................................................................... 366
Bit Rates and SCBRR Settings in Asynchronous Mode ....................................... 367
Bit Rates and SCBRR Settings in Clock Synchronous Mode............................... 369
Maximum Bit Rates for Various Frequencies with Baud Rate Generator
synchronous Mode)............................................................................................... 370
Maximum Bit Rates during External Clock Input (Asynchronous Mode)............ 371
Maximum Bit Rates during External Clock Input (Clock Synchronous Mode) ... 371
Serial Mode Register Settings and SCI Communication Formats ........................ 373
SCSMR and SCSCR Settings and SCI Clock Source Selection ........................... 373
Serial Communication Formats (Asynchronous Mode)........................................ 375
Receive Error Conditions and SCI Operation....................................................... 381
SCI Interrupt Sources............................................................................................ 396
SCSSR Status Flags and Transfer of Receive Data .............................................. 397
Pin Configuration.................................................................................................. 402
Register Settings for the Smart Card Interface...................................................... 408
Relationship of n to CKS1 and CKS0................................................................... 410
Examples of Bit Rate B (Bit/s) for SCBRR Settings (n
Examples of SCBRR Settings for Bit Rate B (Bit/s) (n
Maximum Bit Rates for Frequencies (Smart Card Interface Mode) ..................... 411
Register Set Values and SCK Pin ....................................................................... 412
Smart Card Mode Operating State and Interrupt Sources..................................... 416
SCIF Pins .............................................................................................................. 425
SCSMR2 Settings ................................................................................................. 439
Bit Rates and SCBRR2 Settings ........................................................................... 440
Maximum Bit Rates for Various Frequencies with
Baud Rate Generator (Asynchronous Mode)........................................................ 442
Maximum Bit Rates during External Clock Input (Asynchronous Mode)............ 443
SCSMR2 Settings and SCIF Communication Formats......................................... 446
SCSCR2 and SCSCR2 Settings and SCIF Clock Source Selection...................... 447
Serial Communication Formats ............................................................................ 447
SCIF Interrupt Sources ......................................................................................... 456
List of Multiplexed Pins........................................................................................ 459
Read/Write Operation of the Port A Data Register (PADR)................................. 480
Read/Write Operation of the Port C Data Register (PCDR) ................................. 483
Read/Write Operation of the Port B Data Register (PBDR) ................................ 481
0) ................................ 410
0) ................................ 411