HD6417706 RENESAS [Renesas Technology Corp], HD6417706 Datasheet - Page 286

• Manufacturer Part Number: HD6417706
• Description: Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

8.5.8
When a bus release request (BREQ) is received from an external device, buses are released after
the bus cycle being executed is completed and a bus grant signal (BACK) is output The bus is not
released during burst transfers for cache fills or a write back and TAS instruction execution
between the read cycle and write cycle. Bus arbitration is not executed in multiple bus cycles that
are generated when the data bus width is shorter than the access size; i.e. in the bus cycles when
longword access is executed for the 8-bit memory. At the negation of BREQ, BACK is negated
and bus use is restarted See Appendix B, Pin Functions, for the pin state when the bus is released.
This LSI sometimes needs to retrieve a bus it has released. For example, when memory generates
a refresh request or an interrupt request internally, this LSI must perform the appropriate
processing. This LSI has a bus request signal (IRQOUT) for this purpose. When it must retrieve
the bus, it asserts the IRQOUT signal. Devices asserting an external bus release request receive the
assertion of the IRQOUT signal and negate the BREQ signal to release the bus. This LSI retrieves
the bus and carries out the processing.
IRQOUT
IRQOUT Pin Assertion Conditions:
IRQOUT
IRQOUT
8.5.9
With this LSI, address pin pull-up can be performed when the bus is released by setting the PULA
bit in BCR1 to 1. The address pins are pulled up for a 4-clock period after BACK is asserted.
Figure 8.40 shows the address pin pull-up timing. Similarly, data pin pull-up can be performed by
setting the PULD bit in BCR1 to 1. The data pins should be pulled up when the data bus is not in
use. The data pin pull-up timing for a read cycle is shown in figure 8.41, and the timing for a write
cycle in figure 8.42.
Rev. 4.00, 03/04, page 240 of 660
CKIO
A25 to A0
When a memory refresh request has been generated but the refresh cycle has not yet begun
When an interrupt is generated with an interrupt request level higher than the setting of the
interrupt mask bits (I3 to I0) in the status register (SR). (This does not depend on the SR.BL
bit.)
Bus Arbitration
Bus Pull-Up
Figure 8.40 Pins A25 to A0 Pull-Up Timing
Pull-up
Hi-Z