HD6417706 RENESAS [Renesas Technology Corp], HD6417706 Datasheet - Page 184

• Manufacturer Part Number: HD6417706
• Description: Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

7.2.2
BAMRA is a 32-bit read/write register. BAMRA specifies bits masked in the break address
specified by BARA.
Note: n = 31 to 0.
7.2.3
Break bus cycle register A (BBRA) is a 16-bit read/write register, which specifies (1) CPU cycle
or DMAC cycle, (2) instruction fetch or data access, (3) read or write, and (4) operand size in the
break conditions of channel A.
Rev. 4.00, 03/04, page 138 of 660
Bit
31 to 0 BAMA31 to
Bit
15 to 8
7
6
Bit Name
BAMA0
Break Address Mask Register A (BAMRA)
Break Bus Cycle Register A (BBRA)
Bit Name
—
CDA1
CDA0
Initial Value R/W
All 0
Initial Value
All 0
0
0
R/W
R/W
R
R/W
R/W
Description
Break Address Mask Bit
Specifies bits masked in the channel A break address
bits specified by BARA (BAA31 to BAA0).
0: Break address bit BAAn of channel A is included in
1: Break address bit BAAn of channel A is masked and
the break condition
is not included in the break condition
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
CPU Cycle/DMAC Cycle Select A
Selects the CPU cycle or DMAC cycle as the bus
cycle of the channel A break condition.
00: Condition comparison is not performed
X1: The break condition is the CPU cycle
10: The break condition is the DMAC cycle