MC68HC908LK24 MOTOROLA [Motorola, Inc], MC68HC908LK24 Datasheet - Page 132

• Manufacturer Part Number: MC68HC908LK24
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

Clock Generator Module (CGM)
8.6.5 PLL Reference Divider Select Register
Data Sheet
132
NOTE:
NOTE:
Address:
The PLL reference divider select register (PMDS) contains the
programming information for the modulo reference divider.
RDS[3:0] — Reference Divider Select Bits
The reference divider select bits have built-in protection such that they
cannot be written when the PLL is on (PLLON = 1).
The default divide value of 1 is recommended for all applications.
Reset:
Read:
Write:
Freescale Semiconductor, Inc.
These read/write bits control the modulo reference divider that selects
the reference division factor, R. (See
Programming the
PLLON bit in the PCTL is set. A value of $00 in the reference divider
select register configures the reference divider the same as a value of
$01. (See
initializes the register to $01 for a default divide value of 1.
Figure 8-9. PLL Reference Divider Select Register (PMDS)
For More Information On This Product,
$003B
Bit 7
0
0
Clock Generator Module (CGM)
Go to: www.freescale.com
8.4.7 Special Programming
= Unimplemented
6
0
0
PLL.) RDS[3:0] cannot be written when the
5
0
0
4
0
0
8.4.3 PLL Circuits
RDS3
3
0
Exceptions.) Reset
MC68HC908LJ24/LK24 — Rev. 2
RDS2
2
0
RDS1
1
0
and
MOTOROLA
8.4.6
RDS0
Bit 0
1