MC68HC908LK24 MOTOROLA [Motorola, Inc], MC68HC908LK24 Datasheet - Page 141
MC68HC908LK24
Manufacturer Part Number
MC68HC908LK24
Description
Microcontrollers
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
1.MC68HC908LK24.pdf
(465 pages)
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MC68HC908LJ24/LK24 — Rev. 2
MOTOROLA
PIN LOGIC
RESET
Signal Name
CGMXCLK
CGMPCLK
CGMOUT
PORRST
ICLK
IRST
R/W
IDB
IAB
V
DD
INTERNAL
PULLUP
DEVICE
Internal RC oscillator clock
Buffered version of OSC1 from the oscillator module
The divided PLL output
PLL-based or oscillator-based clock output from CGM module
(Bus clock = CGMOUT ÷ 2)
Internal address bus
Internal data bus
Signal from the power-on reset module to the SIM
Internal reset signal
Read/write signal
SIM RESET STATUS REGISTER
Freescale Semiconductor, Inc.
RESET PIN CONTROL
Table 9-1. Signal Name Conventions
For More Information On This Product,
POR CONTROL
AND PRIORITY DECODE
STOP/WAIT
INTERRUPT CONTROL
CONTROL
CONTROL
Figure 9-1. SIM Block Diagram
CLOCK
System Integration Module (SIM)
Go to: www.freescale.com
CLOCK GENERATORS
RESET
COUNTER
SIM
÷ 2
CONTROL
MASTER
RESET
Description
MODULE STOP
MODULE WAIT
CPU STOP (FROM CPU)
CPU WAIT (FROM CPU)
SIMOSCEN (TO CGM, OSC)
COP CLOCK
ICLK (FROM OSC)
CGMOUT (FROM CGM)
INTERNAL CLOCKS
LVI (FROM LVI MODULE)
ILLEGAL OPCODE (FROM CPU)
ILLEGAL ADDRESS
(FROM ADDRESS MAP DECODERS)
COP (FROM COP MODULE)
INTERRUPT SOURCES
CPU INTERFACE
System Integration Module (SIM)
Introduction
Data Sheet
141
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