MC68HC908LK24 MOTOROLA [Motorola, Inc], MC68HC908LK24 Datasheet - Page 328

• Manufacturer Part Number: MC68HC908LK24
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

Multi-Master IIC Interface (MMIIC)
15.5.5 Multi-Master IIC Data Transmit Register (MMDTR)
Data Sheet
328
Address:
MMTXBE — Multi-Master Transmit Buffer Empty
MMRXBF — Multi-Master Receive Buffer Full
When the MMIIC module is enabled, MMEN = 1, data written into this
register depends on whether module is in master or slave mode.
In slave mode, the data in MMDTR will be transferred to the output circuit
when:
Reset:
Read:
Write:
Figure 15-6. Multi-Master IIC Data Transmit Register (MMDTR)
Freescale Semiconductor, Inc.
This flag indicates the status of the data transmit register (MMDTR).
When the CPU writes the data to the MMDTR, the MMTXBE flag will
be cleared. MMTXBE is set when MMDTR is emptied by a transfer of
its data to the output circuit. Reset sets this bit.
This flag indicates the status of the data receive register (MMDRR).
When the CPU reads the data from the MMDRR, the MMRXBF flag
will be cleared. MMRXBF is set when MMDRR is full by a transfer of
data from the input circuit to the MMDRR. Reset clears this bit.
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For More Information On This Product,
1 = Data transmit register empty
0 = Data transmit register full
1 = Data receive register full
0 = Data receive register empty
the module detects a matched calling address (MMATCH = 1),
with the calling master requesting data (MMSRW = 1); or
the previous data in the output circuit has be transmitted and the
receiving master returns an acknowledge bit, indicated by a
received acknowledge bit (MMRXAK = 0).
MMTD7
$006E
Bit 7
Multi-Master IIC Interface (MMIIC)
1
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MMTD6
6
1
MMTD5
5
1
MMTD4
4
1
MMTD3
3
1
MC68HC908LJ24/LK24 — Rev. 2
MMTD2
2
1
MMTD1
1
1
MOTOROLA
MMTD0
Bit 0
1