MC68HC908LK24 MOTOROLA [Motorola, Inc], MC68HC908LK24 Datasheet - Page 425
MC68HC908LK24
Manufacturer Part Number
MC68HC908LK24
Description
Microcontrollers
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
1.MC68HC908LK24.pdf
(465 pages)
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22.4.4 LVI Trip Selection
22.5 LVI Status Register
MC68HC908LJ24/LK24 — Rev. 2
MOTOROLA
NOTE:
Address:
Reset:
The trip point selection bits, LVISEL[1:0], in the CONFIG2 register select
whether the LVI is configured for 5V or 3 V operation. (See
Configuration Registers
The MCU is guaranteed to operate at a minimum supply voltage. The trip
point (V
Section 24. Electrical Specifications
The LVI status register (LVISR) controls LVI interrupt functions and
indicates if the V
LVIOUT — LVI Output Bit
Read: LVIOUT
Write:
This read-only flag becomes set when the V
V
Freescale Semiconductor, Inc.
TRIPF
For More Information On This Product,
$FE0F
Bit 7
TRIPF
0
trip voltage (see
Go to: www.freescale.com
Table 22-1. LVI Status Register (LVISR)
Low-Voltage Inhibit (LVI)
[5V] or V
= Unimplemented
V
LVIIE
TRIPF
DD
6
0
Table 22-2. LVIOUT Bit Indication
V
V
voltage was detected below the V
DD
DD
< V
TRIPF
V
> V
< V
LVIIF
DD
DD
5
0
TRIPR
TRIPF
(CONFIG).)
Table
< V
[3V]) may be lower than this. (See
TRIPR
LVIIACK
22-2). Reset clears the LVIOUT bit.
4
0
0
for the actual trip point voltages.)
Previous value
3
0
0
LVIOUT
DD
0
1
voltage falls below the
2
0
0
Low-Voltage Inhibit (LVI)
TRIPF
LVI Status Register
1
0
0
Section 5.
level.
Data Sheet
Bit 0
0
0
425
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