MC68HC908LK24 MOTOROLA [Motorola, Inc], MC68HC908LK24 Datasheet - Page 346

• Manufacturer Part Number: MC68HC908LK24
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

Analog-to-Digital Converter (ADC)
16.8.3 ADC Clock Control Register
Data Sheet
346
Address:
The ADC clock control register (ADCLK) selects the clock frequency for
the ADC.
ADIV[2:0] — ADC Clock Prescaler Bits
ADICLK — ADC Input Clock Select Bit
Reset:
Read:
Write:
Freescale Semiconductor, Inc.
ADIV2, ADIV1, and ADIV0 form a 3-bit field which selects the divide
ratio used by the ADC to generate the internal ADC clock.
Table 16-2
should be set to between 32kHz and 2MHz.
ADICLK selects either bus clock or CGMXCLK as the input clock
source to generate the internal ADC clock. Reset selects CGMXCLK
as the ADC clock source.
For More Information On This Product,
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ADIV2
Figure 16-9. ADC Clock Control Register (ADCLK)
ADIV2
X = don’t care
Analog-to-Digital Converter (ADC)
0
0
0
0
0
1
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shows the available clock configurations. The ADC clock
= Unimplemented
ADIV1
Table 16-2. ADC Clock Divide Ratio
0
ADIV1
X
0
0
1
1
ADIV0
0
ADIV0
X
0
1
0
1
ADICLK
0
MODE1
ADC input clock ÷ 1
ADC input clock ÷ 2
ADC input clock ÷ 4
ADC input clock ÷ 8
ADC input clock ÷ 16
R
0
MC68HC908LJ24/LK24 — Rev. 2
ADC Clock Rate
= Reserved
MODE0
1
0
0
MOTOROLA
R
0
0