LAN91C96I_07 SMSC [SMSC Corporation], LAN91C96I_07 Datasheet - Page 69

• Manufacturer Part Number: LAN91C96I_07
• Description: Non-PCI Single-Chip Full Duplex Ethernet Controller
• Manufacturer: SMSC [SMSC Corporation]

Non-PCI Single-Chip Full Duplex Ethernet Controller
Note:
SMSC DS – LAN91C96I
TX EMPTY INT bit - Set whenever the TX FIFO is empty.
AUTO RELEASE - When set, successful transmit packets are not written into completion FIFO, and their
memory is released automatically.
1.
2.
The pointer register is shared by any process accessing the LAN91C96I memory. In order to allow
processes to be interruptible, the interrupting process is responsible for reading the pointer value before
modifying it, saving it, and restoring it before returning from the interrupt.
Typically there would be three processes using the pointer:
1) and 3) also share the usage of the Packet Number Register. Therefore saving and restoring the PNR is
also required from interrupt service routines.
One interrupt per packet: enable TX INT, set AUTO RELEASE=0. The software driver can find the
completion result in memory and process the interrupt one packet at a time. Depending on the
completion code the driver will take different actions. Note that the transmit process is working in
parallel and other transmissions might be taking place. The LAN91C96I is virtually queuing the packet
numbers and their status words.
In this case, the transmit interrupt service routine can find the next packet number to be serviced by
reading the TX FIFO PACKET NUMBER at the FIFO PORTS register. This eliminates the need for
the driver to keep a list of packet numbers being transmitted. The numbers are queued by the
LAN91C96I and provided back to the CPU as their transmission completes.
One interrupt per sequence of packets: Enable TX EMPTY INT and TX INT, set AUTO RELEASE=1.
TX EMPTY INT is generated only after transmitting the last packet in the FIFO. TX INT will be set on
a fatal transmit error allowing the CPU to know that the transmit process has stopped and therefore
the FIFO will not be emptied.
This mode has the advantage of a smaller CPU overhead, and faster memory de-allocation. Note that
when AUTO RELEASE=1 the CPU is not provided with the packet numbers that completed
successfully.
Transmit loading (sometimes interrupt driven)
Receive unloading (interrupt driven)
Transmit Status reading (interrupt driven).
DATASHEET
Page 69
Rev. 03-28-07