LAN91C96I_07 SMSC [SMSC Corporation], LAN91C96I_07 Datasheet - Page 52

• Manufacturer Part Number: LAN91C96I_07
• Description: Non-PCI Single-Chip Full Duplex Ethernet Controller
• Manufacturer: SMSC [SMSC Corporation]

Rev. 03-28-07
3.
Flow of events for an insertion of a transmit packet:
1.
2.
3.
4.
5.
6.
7.
ERCV INT - Early receive interrupt. Set whenever a receive packet is being received, and the number of
bytes received into memory exceeds the value programmed as ERCV THRESHOLD (Bank 3, Offset Ch).
ERCV INT stays set until acknowledged by writing the INTERRUPT ACKNOWLEDGE REGISTER with the
ERCV INT bit set.
EPH INT - Set when the Ethernet Protocol Handler section indicates one out of various possible special
conditions. This bit merges exception type of interrupt sources, whose service time is not critical to the
execution speed of the low level drivers. The exact nature of the interrupt can be obtained from the EPH
Status Register (EPHSR), and enabling of these sources can be done via the Control Register. The
possible sources are:
1.
2.
3.
Any of the above interrupt sources can be masked by the appropriate ENABLE bits in the Control Register.
1) LE ENABLE (Link Error Enable), 2) CR ENABLE (Counter Roll Over), 3) TE ENABLE (Transmit Error
Enable)
EPH INT will only be cleared by the following methods:
1.
The transmit engine is either active or not active
Disable the Transmitter
Remove and release any “transmit done” packets in the TX FIFO
Via polling or an interrupt driven event, determine status of TX IDLE INT bit and wait until this bit is
set. This will determine when the transmitter is truly done with all transmit events.
Remove and store (if any, in software) Packet numbers from the transmit FIFO. (These packets will
later be restored into the TX FIFO after the control frame is inserted into the front of the TX FIFO).
Enable Transmitter
En-queue packet into TX FIFO
En-queue rest of packets, if any, into TX FIFO (restore TX FIFO)
LINK - Link Test transition
CTR_ROL - Statistics counter roll over
TXENA cleared - A fatal transmit error occurred forcing TXENA to be cleared. TX_SUC will be low
and the specific reason will be reflected by the bits:
Clearing the LE ENABLE bit in the Control Register if an EPH interrupt is caused by a LINK_OK
transition.
3.1 TXUNRN - Transmit under-run
3.2 SQET - SQE Error
3.3 LOST CARR - Lost Carrier
3.4 LATCOL - Late Collision
3.5 16COL - 16 collisions
DATASHEET
Page 52
Non-PCI Single-Chip Full Duplex Ethernet Controller
SMSC DS – LAN91C96I