LAN91C96I_07 SMSC [SMSC Corporation], LAN91C96I_07 Datasheet - Page 29

• Manufacturer Part Number: LAN91C96I_07
• Description: Non-PCI Single-Chip Full Duplex Ethernet Controller
• Manufacturer: SMSC [SMSC Corporation]

Non-PCI Single-Chip Full Duplex Ethernet Controller
Chapter 6
SMSC DS – LAN91C96I
The packet format in memory is similar to that in the TRANSMIT and RECEIVE areas. The first word is
reserved for the status word, the next word is used to specify the total number of bytes, and that in turn is
followed by the data area. The data area holds the packet itself, and its length is determined by the byte
count. The packet memory format is word oriented.
CONTROL BYTE
STATUS WORD
BYTE COUNT
DATA AREA
1534 Max
(DECIMAL)
OFFSET
RAM
0
2
4
Packet Format in Buffer memory for
Ethernet
bit15
RESERVED
Written by CSMA upon transmit
completion (see Status Register)
Written by CPU
Written/modified by CPU
Written by CPU to control
ODD/EVEN data bytes
2nd Byte
Figure 6.1 – Data Packet Format
CONTROL BYTE
Last Byte
DATASHEET
TRANSMIT PACKET
Page 29
STATUS WORD
DATA AREA
BYTE COUNT (always even)
LAST DATA BYTE (if odd)
Written by CSMA upon receive
completion (see RX Frame
Status Word)
Written by CSMA
Written by CSMA
Written by CSMA. Also has
ODD/EVEN bit
RECEIVE PACKET
1st Byte
bit0
Rev. 03-28-07