LAN91C96I_07 SMSC [SMSC Corporation], LAN91C96I_07 Datasheet - Page 3

• Manufacturer Part Number: LAN91C96I_07
• Description: Non-PCI Single-Chip Full Duplex Ethernet Controller
• Manufacturer: SMSC [SMSC Corporation]

Non-PCI Single-Chip Full Duplex Ethernet Controller
Table of Contents
Chapter 1
Chapter 2
Chapter 3
3.1
Chapter 4
4.1
Chapter 5
5.1
5.2
5.3
5.4
Chapter 6
Chapter 7
7.1
7.2
Chapter 8
8.1
8.2
8.3
8.4
8.5
8.6
Chapter 9
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
9.9
9.10
9.11
9.12
9.13
9.14
9.15
Chapter 10
10.1
10.2
Chapter 11
11.1
11.2
Chapter 12
SMSC DS – LAN91C96I
7.2.1
Local Bus vs. Pin Requirements ....................................................................................................... 12
Buffer Symbols .................................................................................................................................. 17
Buffer Memory ................................................................................................................................... 20
Interrupt Structure ............................................................................................................................. 26
Reset Logic........................................................................................................................................ 27
Power Down Logic States ................................................................................................................. 27
I/O Space Access.............................................................................................................................. 33
I/O Space Registers Description ....................................................................................................... 34
Typical Flow Of Events For Transmit (Auto Release =0).................................................................. 60
Typical Flow of Events for Transmit (Auto Release = 1)................................................................... 61
Typical Flow Of Events For Receive ................................................................................................. 62
Memory Partitioning .......................................................................................................................... 68
Interrupt Generation .......................................................................................................................... 68
Power Down ...................................................................................................................................... 70
Memory Management Unit ................................................................................................................ 72
Arbiter ................................................................................................................................................ 72
Bus Interface ..................................................................................................................................... 73
Wait State Policy ............................................................................................................................... 73
Arbitration Considerations ................................................................................................................. 74
DMA Block......................................................................................................................................... 74
Packet Number FIFOs....................................................................................................................... 75
CSMA Block ...................................................................................................................................... 76
Network Interface .............................................................................................................................. 78
10BASE-T ...................................................................................................................................... 78
AUI ................................................................................................................................................. 78
Physical Interface........................................................................................................................... 79
Transmit Functions......................................................................................................................... 79
Transmit Drivers............................................................................................................................. 79
Receive Functions.......................................................................................................................... 79
Diagnostic LEDs............................................................................................................................. 82
Bus Clock Considerations.............................................................................................................. 82
Maximum Guaranteed Ratings*..................................................................................................... 84
DC Electrical Characteristics ......................................................................................................... 85
Bank Select Register ..............................................................................................................................34
General Description ............................................................................................................. 5
Overview ............................................................................................................................... 6
Pin Configurations ............................................................................................................... 9
Description of Pin Functions ............................................................................................. 14
Functional Description....................................................................................................... 19
Packet Format in Buffer memory for Ethernet............................................................... 29
Registers Map in I/O Space............................................................................................... 32
Theory of Operation .......................................................................................................... 58
Functional Description of the Blocks................................................................................ 72
Board Setup Information ............................................................................................... 81
Operation Description .................................................................................................... 84
Timing Diagrams ............................................................................................................ 91
DATASHEET
Page 3
Rev. 03-28-07