LAN91C96I_07 SMSC [SMSC Corporation], LAN91C96I_07 Datasheet - Page 41

• Manufacturer Part Number: LAN91C96I_07
• Description: Non-PCI Single-Chip Full Duplex Ethernet Controller
• Manufacturer: SMSC [SMSC Corporation]

Non-PCI Single-Chip Full Duplex Ethernet Controller
Note 7.1 Bits 11, 10 and 9 are read only bits used by the software driver to transparently run on different controllers
SMSC DS – LAN91C96I
of EN16*
function
The contents of MIR as well as the low byte of MCR are specified in 256* M bytes. The multiplier M is
determined by bits 11, 10 and 9 as follows:
of the LAN9000 family.
I/O SPACE - BANK1
The Configuration Register holds bits that define the device configuration and are not expected to change
during run-time. This register is part of the EEPROM saved setup in Local Bus mode only.
NO WAIT - When set, does not request additional wait states. An exception to this are accesses to the
Data Register if not ready for a transfer. When clear, negates IOCHRDY for two to three 20MHz clocks on
any cycle to the LAN91C96I.
FULL STEP - This bit is used to select the signaling mode for the AUI port. When set the AUI port uses full
step signaling. Defaults low to half step signaling. This bit is only meaningful when AUI SELECT is high.
SET SQLCH - When set, the squelch level used for the 10BASE-T receive signal is 240mV. When clear
the receive squelch level is 400mV. Defaults low.
AUI SELECT - When set the AUI interface is used, when clear the 10BASE-T interface is used. Defaults
low.
16BIT - Used in conjunction with EN16* and IO is 8 to define the width of the system bus. If the EN16* pin
is low, this bit is forced high. Otherwise the bit defaults low and can be programmed by the host CPU.
DIS LINK - This bit is used to disable the 10BASE-T link test functions. When this bit is high the
LAN91C96I disables link test functions by not generating nor monitoring the network for link pulses. In this
mode the LAN91C96I will transmit packets regardless of the link test, the EPHSR LINK_OK bit will be set
and the LINK LED will stay on. When low the link test functions are enabled. If the link status indicates
FAIL, the EPHSR LINK_OK bit will be low, while transmit packets enqueued will be processed by the
LAN91C96I, transmit data will not be sent out to the cable.
16BIT
OFFSET
pin
0
0
0
LAN91C90
FUTURE
FUTURE
FUTURE
DIS LINK
FEAST
DEVICE
X
0
CONFIGURATION REGISTER
BIT 11
X
1
0
0
0
1
1
DATASHEET
NAME
BIT 10
Reserved
WAIT
1
0
1
0
0
NO
1
0
Page 41
BIT 9
0
1
1
0
1
X
0
16
M
2
1
4
8
READ/WRITE
STEP
FULL
MAX MEMORY SIZE
0
0
SEL1
TYPE
INT
256
256
(Note 7.1)
(Note 7.1)
(Note 7.1)
(Note 7.1)
256k
512k
1M
SQLCH
SET
2=128k
1=64k
0
0
SEL0
INT
256
256
SYMBOL
SELECT
CR
AUI
0
X
Rev. 03-28-07