LAN91C96I_07 SMSC [SMSC Corporation], LAN91C96I_07 Datasheet - Page 27

• Manufacturer Part Number: LAN91C96I_07
• Description: Non-PCI Single-Chip Full Duplex Ethernet Controller
• Manufacturer: SMSC [SMSC Corporation]

Non-PCI Single-Chip Full Duplex Ethernet Controller
5.3
5.4
SMSC DS – LAN91C96I
RESET pin
ECOR
Register
SRESET bit
SOFT RST
Reset Logic
The pins and bits involved in the different reset mechanisms are:
RESET - Input Pin
SRESET - Soft Reset bit in ECOR, or the SRESET bit
SOFT RST - EPH Soft Reset bit in RCR
Power Down Logic States
Tables Table 5.5 and Table 5.6 describe the power down states of the LAN91C96I. The pins and bits
involved in power down are:
1.
2.
3.
4.
PWRDWN/TXCLK - Input pin valid when XENDEC is not zero (0).
Pwrdwn bits in ECSR
Enable Function bit in ECOR
PWRDN - Legacy power down bit in Control Register.
All internal logic
The Ethernet controller function except for
the bit itself. Setting this bit also lowers
the nIREQ/READY line. When cleared,
the nIREQ/READY line is raised.
The Ethernet controller itself except for
the IA, CONF and BASE registers.
RESETS THE FOLLOWING FUNCTIONS
DATASHEET
Table 5.4 – Reset Logic
Page 27
LOCAL BUS
SAMPLES
MODE
Yes
No
No
TRIGGERS
EEPROM
READ
Yes
Yes
No
Rev. 03-28-07