LAN91C96I_07 SMSC [SMSC Corporation], LAN91C96I_07 Datasheet - Page 61

• Manufacturer Part Number: LAN91C96I_07
• Description: Non-PCI Single-Chip Full Duplex Ethernet Controller
• Manufacturer: SMSC [SMSC Corporation]

Non-PCI Single-Chip Full Duplex Ethernet Controller
8.2
SMSC DS – LAN91C96I
1 ISSUE ALLOCATE MEMORY FOR TX - N
2 WAIT
3 LOAD TRANSMIT DATA - Copy the TX packet
4 ISSUE "ENQUEUE PACKET NUMBER TO TX
5
6
7
8 a)
BYTES - the MMU attempts to allocate N bytes
of RAM.
CODE - Poll until the ALLOC INT bit is set or
enable its mask bit and wait for the interrupt.
The TX packet number is now at the Allocation
Result Register.
number into the Packet Number Register. Write
the Pointer Register, then use a block move
operation from the upper layer transmit queue
into the Data Register.
FIFO" - This command writes the number
present in the Packet Number Register into the
TX FIFO. The transmission is now enqueued.
No further CPU intervention is needed until a
transmit interrupt is generated.
b)
Typical Flow of Events for Transmit (Auto Release = 1)
SERVICE INTERRUPT – Read Interrupt
Status Register, exit the interrupt service
routine.
Option 1) Release the packet.
Option 2) Check the transmit status in the
EPH STATUS Register, write the packet
number of the current packet to the Packet
Number Register, re-enable TXENA, then
go to step 4 to start the TX sequence again.
FOR
SUCCESSFUL
S/W DRIVER
COMPLETION
DATASHEET
Page 61
The enqueued packet will be transferred to the
MAC block as a function of TXENA (nTCR) bit
and of the deferral process (1/2 duplex mode
only) state.
Transmit pages are released by transmit
completion.
a)
b)
The MAC generates a TXEMPTY interrupt
upon a completion of a sequence of
enqueued packets.
If a TX failure occurs on any packets, TX
INT is generated and TXENA is cleared,
transmission sequence stops. The packet
number of the failure packet is presented at
the TX FIFO PORTS Register.
MAC SIDE
Rev. 03-28-07